Datasheet

ManualsBrandsANALOG DEVICES ManualsClock & Timing ICsLFCSP-32-VQ

Continuous Rate 10 Mb/s to 675 Mb/s

Clock and Data Recovery IC

Data Sheet

ADN2816

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Tel: 781.329.4700

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FEATURES

Serial data input: 10 Mb/s to 675 Mb/s

Exceeds SONET requirements for jitter transfer/

generation/tolerance

Patented clock recovery architecture

No reference clock required

Loss-of-lock indicator

C® interface to access optional features

Single-supply operation: 3.3 V

Low power: 366 mW typical

5 mm × 5 mm 32-lead LFCSP, Pb free

APPLICATIONS

SONET OC-1/-3/-12 and all associated FEC rates

Fibre Channel, ESCON, Fast Ethernet, SDI

WDM transponders

Regenerators/repeaters

Test equipment

Broadband crossconnects and routers

GENERAL DESCRIPTION

The ADN2816 provides the receiver functions of quantization

and clock and data recovery for continuous data rates from

10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all

data rates without the need for an external reference clock or

programming. All SONET jitter requirements are met,

including jitter transfer, jitter generation, and jitter tolerance.

All specifications are quoted for −40°C to +85°C ambient

temperature, unless otherwise noted.

The ADN2816 is available in a compact 5 mm × 5 mm 32-lead

LFCSP.

FUNCTIONAL BLOCK DIAGRAM

04948-0-001

LOL

DATAOUTP/

DATAOUTN

DRVEE DVCCDRVCC

DVEE

ADN2816

CLKOUTP/

CLKOUTN

VCC VEECF1 CF2

NIN

VREF

BUFFER

VCO

PHASE

SHIFTER

PHASE

DETECT

FREQUENCY

DETECT

DATA

RE-TIMING

LOOP

FILTER

LOOP

FILTER

REFCLKP/REFCLKN

(OPTIONAL)

Figure 1.

Summary of content (24 pages)

PAGE 1
Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC ADN2816 Data Sheet FEATURES GENERAL DESCRIPTION Serial data input: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.
PAGE 2
ADN2816 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ....................................................................................... 1 Functional Description .................................................................. 14 General Description .....................................................
PAGE 3
Data Sheet ADN2816 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1.
PAGE 4
ADN2816 Data Sheet JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Conditions Min OC-12 OC-3 OC-12 OC-3 OC-12, 12 kHz to 5 MHz OC-3, 12 kHz to 1.
PAGE 5
Data Sheet ADN2816 OUTPUT AND TIMING SPECIFICATIONS Table 3.
PAGE 6
ADN2816 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 7
Data Sheet ADN2816 TIMING CHARACTERISTICS CLKOUTP TH 04948-0-002 TS DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOH VOS 04948-0-032 |VOD| VOL Figure 3. Differential Output Specifications 5mA RLOAD 100 VDIFF 100 SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev.
PAGE 8
ADN2816 Data Sheet 32 VCC 31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADN2816* TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE 04948-0-004 PIN 1 INDIC ATOR NC 9 REFCLKP 10 REFCLKN 11 VCC 12 VEE 13 CF2 14 CF1 15 LOL 16 VCC 1 VCC 2 VREF 3 NIN 4 PIN 5 NC 6 NC 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 5. Pin Configuration Table 5.
PAGE 9
Data Sheet ADN2816 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 A5 MSB = 1 SET BY PIN 19 0 0 0 0 0 X 0 = WR 1 = RD 04948-0-007 R/W CTRL. SLAVE ADDRESS [6...0] S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 04948-0-008 Figure 6.
PAGE 10
ADN2816 Data Sheet Table 6.
PAGE 11
Data Sheet ADN2816 JITTER SPECIFICATIONS Jitter Generation The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. For SONET devices, the jitter generated must be less than 0.01 UI rms, and must be less than 0.1 UI p-p. Jitter Transfer The jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs. the frequency.
PAGE 12
ADN2816 Data Sheet THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function.
PAGE 13
Data Sheet ADN2816 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and therefore the phase shifter takes on the burden of tracking the input jitter.
PAGE 14
ADN2816 Data Sheet FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION Once LOL is deasserted, the frequency-locked loop is turned off. The PLL/DLL pulls in the VCO frequency the rest of the way until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pin 14 and Pin 15. A 0.47 µF ± 20%, X7R ceramic chip capacitor with < 10 nA leakage current is recommended.
PAGE 15
Data Sheet ADN2816 The CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates in the normal operating mode, that is, it is asserted only when the ADN2816 is in acquisition mode and deasserts when the ADN2816 has reacquired lock. HARMONIC DETECTOR The ADN2816 provides a harmonic detector, which detects whether or not the input data has changed to a lower harmonic of the data rate that the VCO is currently locked onto. For example, if the input data instantaneously changes from OC-12, 622.
PAGE 16
ADN2816 Data Sheet REFERENCE CLOCK (OPTIONAL) A reference clock is not required to perform clock and data recovery with the ADN2816. However, support for an optional reference clock is provided. The reference clock can be driven differentially or single-ended. If the reference clock is not being used, then REFCLKP should be tied to VCC, and REFCLKN can be left floating or tied to VEE (the inputs are internally terminated to VCC/2). See Figure 16 through Figure 18 for sample configurations.
PAGE 17
Data Sheet ADN2816 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF, where DIV_FREF represents the divided-down reference referred to the 10 MHz to 20 MHz band. For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mb/s, then CTRLA[7:6] is set to [01] to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5, because 622.
PAGE 18
ADN2816 Data Sheet Additional Features Available via the I2C Interface Coarse Data Rate Readback System Reset The data rate can be read back over the I2C interface to approximately ±10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The eight MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0].
PAGE 19
Data Sheet ADN2816 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 24, which supplies power to the high speed CLKOUTP/CLKOUTN and DATAOUTP/ DATAOUTN output buffers. Refer to Figure 19 for the recommended connections. Proper RF PCB design techniques must be used for optimal performance.
PAGE 20
ADN2816 Data Sheet Transmission Lines Choosing AC Coupling Capacitors Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz).
PAGE 21
Data Sheet ADN2816 VCC V1 CIN ADN2816 V2 PIN COUT + DATAOUTP 50 TIA V1b CIN V2b VREF CDR BUFFER DATAOUTN 50 COUT – NIN V1 1 2 3 4 V1b V2 VREF V2b VTH VDIFF NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3.
PAGE 22
ADN2816 Data Sheet COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 FMID 5.3745e+06 5.3741e+06 5.4793e+06 5.5912e+06 5.7111e+06 5.8391e+06 5.9760e+06 6.1215e+06 6.2780e+06 6.4565e+06 6.6391e+06 6.8372e+06 7.0520e+06 7.2868e+06 7.5424e+06 7.8220e+06 7.6663e+06 7.6659e+06 7.8217e+06 7.9880e+06 8.
PAGE 23
Data Sheet Code 192 193 194 195 196 197 198 199 200 201 FMID 3.4397e+08 3.4394e+08 3.5067e+08 3.5783e+08 3.6551e+08 3.7370e+08 3.8247e+08 3.9177e+08 4.0179e+08 4.1322e+08 ADN2816 Code 202 203 204 205 206 207 208 209 210 211 FMID 4.2490e+08 4.3758e+08 4.5133e+08 4.6636e+08 4.8272e+08 5.0061e+08 4.9064e+08 4.9062e+08 5.0059e+08 5.1123e+08 Code 212 213 214 215 216 217 218 219 220 221 Rev. C | Page 23 of 24 FMID 5.2267e+08 5.3485e+08 5.4794e+08 5.6195e+08 5.7706e+08 5.9423e+08 6.1189e+08 6.3098e+08 6.
PAGE 24
ADN2816 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 22.