Datasheet

ADN2816 Data Sheet
Rev. C | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04948-0-004
VCC 1
VCC 2
VREF 3
PIN 1
INDIC ATOR
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 NC
21 SDA
32 VCC
20 SCK
19 SADDR5
18 VCC
17 VEE
NC 9
REFCLKP 10
REFCLKN 11
VCC 12
VEE 13
CF2 14 CF1 15
LOL 16
NIN 4
PIN 5
NC 6
NC 7
VEE 8
31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN
ADN2816*
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 VCC AI Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6, 7 NC No Connect.
8 VEE P GND for Limiting Amplifier, LOS.
9
NC
No Connect.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14
CF2
AO
Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I
2
C Clock Input.
21 SDA DI I
2
C Data Input.
22 NC No Connect.
23 VEE P Output Buffer, I
2
C GND.
24 VCC P Output Buffer, I
2
C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27
SQUELCH
DI
Disable Clock and Data Outputs. Active high. LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 VCC AI Connect to VCC.
Exposed Pad Pad P Connect to GND. Works as a heat sink.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.