Datasheet

ADP151 Data Sheet
Rev. E | Page 12 of 24
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP151 is designed for operation with small, space-saving
ceramic capacitors but can function with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of 1 µF
capacitance with an ESR of 1 Ω or less is recommended to ensure
the stability of the ADP151. Transient response to changes in load
current is also affected by output capacitance. Using a larger value
of output capacitance improves the transient response of the
ADP151 to large changes in load current. Figure 28 shows the
transient responses for an output capacitance value of 1 µF.
CH1 200mA CH2 50mV M20µs A CH1 64mA
T 10.00%
1
2
T
LOAD CURRENT
V
OUT
08627-026
Figure 28. Output Transient Response, C
OUT
= 1 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces
the circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 µF of output capacitance is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the
ADP151, as long as it meets the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have an
adequate dielectric to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recommended.
Y5V and Z5U dielectrics are not recommended, due to their
poor temperature and dc bias characteristics.
Figure 29 depicts the capacitance vs. voltage bias characteristic
of an 0402, 1 µF, 10 V X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0 2 4 6 8 10
CAPACITANCE (µF)
VOLTAGE BIAS
08627-027
Figure 29. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst-case capacitance, accounting
for capacitor variation over temperature, component tolerance,
and voltage.
C
EFF
= C
BIAS
× (1 − TEMPCO) × (1 − TOL) (1)
where:
C
BIAS
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C
BIAS
is 0.94 μF at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields
C
EFF
= 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over tempera-
ture and tolerance at the chosen output voltage.
To guarantee the performance of the ADP151, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.