Datasheet

Data Sheet ADP1649
Rev. 0 | Page 27 of 28
PCB LAYOUT
Poor layout can affect performance, causing electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
problems, ground bounce, and power losses. Poor layout can
also affect regulation and stability. Figure 42 shows an optimized
layout implemented using the following guidelines:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and large currents.
• Route the trace from the inductor to the SW pin, providing
as wide a trace as possible. The easiest path is through the
center of the output capacitor.
• Route the LED_OUT path away from the inductor and the
SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side
to help with thermal dissipation.
• Use a ground plane with two to three vias connected to the
component side ground near the output capacitor to
reduce noise interference on sensitive circuit nodes.
Analog Devices applications engineers can be contacted
through the Analog Devices sales team to discuss different
layouts based on system design constraints.
Figure 42. Layout of the ADP1649 Driving a High Power White LED (WLCSP)
DIGITAL
INPUT/
OUTPUT
Li-ION +
Li-ION +
PGND
C1
L1
INDUCTOR
LED
ANODE
C2
AREA = 16.4mm
2
10779-042