Datasheet

ADP170/ADP171 Data Sheet
Rev. C | Page 12 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP170/ADP171 are designed for operation with small,
space-saving ceramic capacitors but will function with most
commonly used capacitors as long as care is taken with regard
to the effective series resistance (ESR) value. The ESR of the
output capacitor affects the stability of the LDO control loop.
A minimum of 1 μF capacitance with an ESR of 1 Ω or less is
recommended to ensure stability of the ADP170/ADP171. The
transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP170/ADP171 to
large changes in load current. Figure 27 and Figure 28 show the
transient responses for output capacitance values of 1 μF and
4.7 μF, respectively.
07716-125
CH1 200mA Ω CH2 50.0mV
B
W
M200ns A CH1 112mA
1
2
T 500.000ns
I
LOAD
V
OUT
V
OUT
= 1.8V
C
IN
= C
OUT
= 1µF
1mA TO 300mA LOAD STEP,
2.5A/µs
Figure 27. Output Transient Response, C
OUT
= 1 μF
07716-126
CH1 200mA Ω CH2 50.0mV
B
W
M200ns A CH1 108mA
1
2
T 500.000ns
I
LOAD
V
OUT
V
OUT
= 1.8V
C
IN
= C
OUT
= 4.7µF
1mA TO 300mA LOAD STEP,
2.5A/µs
Figure 28. Output Transient Response, C
OUT
= 4.7 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces the
circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 μF of output capacitance is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the
ADP170/ADP171, as long as it meets the minimum capacitance
and maximum ESR requirements. Ceramic capacitors are manu-
factured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. A X5R or X7R
dielectric with a voltage rating of 6.3 V or 10 V is recommended.
The Y5V and Z5U dielectrics are not recommended, due to their
poor temperature and dc bias characteristics.
Figure 29 depicts the capacitance vs. bias voltage characteristics
of a 0402, 1 μF, 10 V X5R capacitor. The variance of a capacitor
is strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
will exhibit less capacitance variance over bias voltage. The
temperature variation of the X5R dielectric is about ±15% over
the −40°C to +85°C temperature range and is not a function of
package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0246810
07716-025
CAPACITANCE (µF)
BIAS VOLTAGE (V)
Figure 29. Capacitance vs. Bias Voltage Characteristics
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
EFF
= C
BIAS
× (1 − TEMPCO) × (1 − TOL) (1)
where:
C
BIAS
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.