Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - voltage regulators - DC DC switch controllers QSOP 24

PWM, Step-Down DC-to-DC Controller

with Margining and Tracking

Data Sheet

ADP1822

Rev. D

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FEATURES

Wide power input voltage range: 1 V to 24 V

Chip supply voltage range: 3.7 V to 5.5 V

Wide output voltage range: 0.6 V to 85% of input voltage

1% accuracy, 0.6 V reference voltage

Output voltage margining control

Output voltage tracking

All N-channel MOSFET

300 kHz, 600 kHz, or up to 1.2 MHz synchronized frequency

No current sense resistor required

Power-good output

Programmable soft start with reverse current protection

Current-limit protection

Thermal overload protection

Overvoltage protection

Undervoltage lockout

1 µA shutdown supply current

Small, 24-lead QSOP package

APPLICATIONS

Telecommunications and networking systems

High performance servers

Medical imaging systems

DSP core power supplies

Microprocessor core power supplies

Mobile communication base stations

Distributed power

GENERAL DESCRIPTION

The ADP1822 is a versatile and inexpensive synchronous voltage-

mode PWM step-down controller. It drives an all N-channel power

stage to regulate an output voltage as low as 0.6 V.

The ADP1822 regulated output can track another power supply

and can be dynamically adjusted up or down with the controller’s

margining-control inputs, making it ideal for high reliability

applications. It is well suited for a wide range of high power

applications, such as DSP power and processor core power in

telecommunications, medical imaging, high performance

servers, and industrial applications. It operates from a 3.7 V to

5.5 V supply with power input voltage ranging from 1.0 V to 24 V.

The ADP1822 can operate at any frequency between 300 kHz

and 1.2 MHz, either by synchronizing with an external source

or an internally generated, logic-controlled clock of 300 kHz or

600 kHz. It includes an adjustable soft start to allow sequencing

and quick power-up while preventing input inrush current. Output

reverse-current protection at startup prevents excessive output

voltage excursions. The adjustable, virtually lossless current-

limit scheme reduces external part count and improves efficiency.

The ADP1822 operates over the −40°C to +125°C junction

temperature range and is available in a 24-lead QSOP package.

LOAD CURRENT (A)

EFFICIENCY (%)

2 4 6 8 10 12 14

1.8V OUTPUT

3.3V OUTPUT

05311-006

Figure 1. Efficiency vs. Load Current, 5 V Input

BIAS INPUT

1µF

10Ω

FREQ

SYNC

MAR

MSEL

COMP

100nF

IRF3711

1µH

180µF

20V

1000µF

BST

PGND

TRKP

TRKN

MDN

MUP

0.1µF

PVCC

ADP1822

6.18kΩ

POWER INPUT

2.25V TO 24V

05311-001

OUTPUT

1.8V, 15A

1µF

80.6kΩ

309pF

AGND

DGND

TRACKING

SIGNAL INPUT

2.2pF

1nF

15pF

158kΩ

316kΩ

CMOSH-3

20kΩ

10kΩ

VCC

PWGD

CSL

SHDN

Figure 2. Typical Operating Circuit

Summary of content (24 pages)

PAGE 1
PWM, Step-Down DC-to-DC Controller with Margining and Tracking ADP1822 Data Sheet FEATURES The ADP1822 regulated output can track another power supply and can be dynamically adjusted up or down with the controller’s margining-control inputs, making it ideal for high reliability applications. It is well suited for a wide range of high power applications, such as DSP power and processor core power in telecommunications, medical imaging, high performance servers, and industrial applications.
PAGE 2
ADP1822 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Switching Frequency Control ................................................... 13 Applications ....................................................................................... 1 Compensation............................................................................. 13 General Description ................................................................
PAGE 3
Data Sheet ADP1822 SPECIFICATIONS VVCC = VPVCC = VSHDN = VFREQ = VTRKN = 5 V, SYNC = MAR = MSEL = GND. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1.
PAGE 4
ADP1822 Parameter TRACKING Tracking Comparator Input Offset Tracking Comparator Delay Tracking Comparator Common-Mode Input Voltage Range TRKP Pull-Up Resistance TRKN Pull-Down Resistance LOGIC THRESHOLDS (SHDN, SYNC, FREQ, MAR, MSEL) Input High Voltage Input Low Voltage SYNC, FREQ Input Leakage Current SHDN, MAR, MSEL Pull-Down Resistance THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PWGD OUTPUT FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Underv
PAGE 5
Data Sheet ADP1822 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC, SHDN, SYNC, FREQ, COMP, SS, FB, TRKP, TRKN, MAR, MSEL, MUP, and MDN to GND; PVCC to PGND; BST to SW BST to GND CSL to GND DH to GND DL to PGND SW to GND PGND to GND θJA, 2-Layer (SEMI Standard Board) θJA, 4-Layer (JEDEC Standard Board) Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Maximum Soldering Lead Temperature Rating −0.3 V to +6 V −0.3 V to +30 V −1 V to +30 V (VSW − 0.
PAGE 6
ADP1822 Data Sheet SIMPLIFIED BLOCK DIAGRAM SHDN ADP1822 VCC UVLO GND THERMAL SHUTDOWN LOGIC FAULT BST DH S FREQ Q SW OSCILLATOR SYNC PWM PVCC COMP R MAR Q DL DECODE MSEL VCC PGND CSL MUP MDN TRKP DGND TRKN FB VREF 100kΩ 0.8V UV PWGD 2.5kΩ FAULT UVLO THSD Figure 3. Simplified Block Diagram Rev.
PAGE 7
Data Sheet ADP1822 BST 1 24 NC DH 2 23 PVCC SW 3 22 DL SYNC 4 21 PGND FREQ 5 20 CSL MAR 6 19 VCC TRKN 7 TRKP 8 SHDN ADP1822 TOP VIEW (Not to Scale) 18 MUP 17 MDN 9 16 MSEL PWGD 10 15 COMP DGND 11 14 FB GND 12 13 SS NC = NO CONNECT 05311-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. ADP1822 Pin Configuration Table 3. Pin Function Descriptions Pin No.
PAGE 8
ADP1822 Pin No. 17 Mnemonic MDN 18 MUP 19 VCC 20 CSL 21 22 PGND DL 23 PVCC 24 NC Data Sheet Description Margin Down Input. Connect a resistor from MDN to the output voltage to set the low margining voltage. See the Setting the Voltage Margin section. Margin Up Input. Connect a resistor from MUP to GND to set the high margining voltage. See the Setting the Voltage Margin section. Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with 0.
PAGE 9
Data Sheet ADP1822 TYPICAL PERFORMANCE CHARACTERISTICS 97 0.6003 96 0.6002 3.3V OUTPUT FEEDBACK VOLTAGE (V) 95 EFFICIENCY (%) 94 93 1.8V OUTPUT 92 91 90 0.6001 0.6000 0.5999 0.5998 89 87 0 2 4 6 8 10 12 14 0.5996 –50 16 LOAD CURRENT (A) –30 –10 10 30 50 70 90 110 TEMPERATURE (°C) Figure 5. Efficiency vs. Load Current, VIN = 5 V, VOUT = 3.3 V, 1.8 V Figure 8. FB Regulation Voltage vs. Temperature 94 700 600 3.3V OUTPUT 90 88 1.
PAGE 10
ADP1822 Data Sheet OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (50mV/DIV) SHDN (5V/DIV) INPUT VOLTAGE (5V/DIV) Figure 11. Power-On Response 05311-015 05311-012 PWGD (5V/DIV) Figure 14. Line Transient Response, 10 V to 16 V OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE (100mV/DIV) SHDN (5V/DIV) MAR VOLTAGE (5V/DIV) Figure 12. Power-On Response, Prebiased Output 05311-016 05311-013 PWGD (5V/DIV) Figure 15.
PAGE 11
Data Sheet ADP1822 TRACKING VOLTAGE (1V/DIV) 05311-018 OUTPUT VOLTAGE (1V/DIV) Figure 17. Output Voltage Tracking Response Rev.
PAGE 12
ADP1822 Data Sheet THEORY OF OPERATION The ADP1822 is a versatile, economical, synchronous-rectified, fixed frequency, voltage-mode, pulse-width modulated (PWM) step-down controller capable of generating an output voltage as low as 0.6 V. It is ideal for a wide range of high power applications, such as DSP and processor core power in telecommunications, medical imaging, and industrial applications. The ADP1822 controller runs from 3.7 V to 5.5 V and accepts a power input voltage between 1.0 V and 24 V.
PAGE 13
Data Sheet ADP1822 If the output voltage is precharged prior to turn-on, the ADP1822 prevents reverse inductor current that would discharge the output voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage, the reverse current is re-enabled to allow the output voltage regulation to be independent of load current. To override the soft start feature, leave SS unconnected. This allows the output voltage to rise as quickly as possible and eliminates the soft start period.
PAGE 14
ADP1822 Data Sheet APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR The input capacitor absorbs the switched input current of the dc-to-dc converter, allowing the input source to deliver smooth dc current. Choose an input capacitor whose impedance at the switching frequency is lower than the input source impedance. Use low equivalent series resistance (ESR) capacitors, such as low ESR tantalum, ceramic, or organic electrolyte (such as Sanyo OS-CON) types.
PAGE 15
Data Sheet ADP1822 When fESRZ is approximately the same as the switching frequency, the square-root sum of the squares of the two ripples applies, or ΔVOUT   ΔI L ≅ [ΔI L (ESR)] +    8(COUT )( f SW )  2 2 (6) loss exceeds the MOSFET rating, or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel.
PAGE 16
ADP1822 RHI = I LPK Data Sheet VOUT RONWC RLO (14) − 42 μA where: IPKFOLDBACK is the desired short-circuit peak inductor current limit. ILPK is the peak inductor current limit during normal operation and is also used in Equation 12. VIN M1 DH L VOUT + DL M2 RLO CSL  R  V RDN =  TOP  1 − FB − K MDN   K MDN   VOUT  where: RDN is the down-margin resistor. RTOP is the top voltage divider resistor from FB to the output voltage. VFB is the 0.6 V feedback voltage.
PAGE 17
Data Sheet ADP1822 then use both the ESR zero and feed-forward zeros to stabilize the regulator (see the Compensation Using Both the ESR and Feed-Forward Zeros section). In all three cases, it is sometimes beneficial, although not required, to add an additional compensation capacitor, CC2, from COMP to FB to reduce high frequency noise. This capacitor forms an extra pole in the loop response.
PAGE 18
ADP1822 Data Sheet Choose the compensation capacitor to set the compensation zero, fZC, to the lesser of 1/4 of the crossover frequency or 1/2 of the LC resonant frequency, or f ZC = f CO f SW 1 = = 4 40 2π(CCOMP )(RCOMP ) (36) RCOMP = (RTOP )(VRAMP )( f ZFF )( f CO ) VIN ( f LC )2 where fZFF is the feed-forward zero frequency and is 1/7 of the crossover frequency. Simplify the following equation: RCOMP ≅ 0.
PAGE 19
Data Sheet ADP1822 or where DSYNC is the duty cycle of the synchronization waveform. t SS 100 kΩ(C SS )  0.6 V  = 1.386 = − ln1 −  0.8 V   (57) Solving for CSS and combining constants, CSS = (7.213 × 10−6)tSS SETTING THE OUTPUT VOLTAGE TRACKING (58) SYNCHRONIZING THE CONVERTER The dc-to-dc converter switching can be synchronized to an external signal. This allows multiple ADP1822 converters to be operated at the same frequency to prevent frequency beating or other interactions.
PAGE 20
ADP1822 Data Sheet APPLICATION CIRCUITS CMOSH-3 VCC BST PVCC ADP1822 3.01kΩ CSL FREQ DL SYNC 3× IRF3711 1µH 4× 1000µF, 4V 2.2pF OUTPUT 1.8V, 15A 20kΩ PGND PWGD FB MAR TRKP MSEL 10kΩ 1nF 158kΩ TRKN MDN COMP 309pF DH SW SHDN 80.6kΩ INPUT 5V 0.1µF 1µF 15pF 2× 180µF 20V SS AGND DGND MUP 316kΩ 100nF TRACKING SIGNAL INPUT 05311-019 1µF 10Ω 10Ω Figure 21. Typical Application Circuit, 5 V Input CMOZ5V6 CMST2222A 1.2kΩ CMOSH-3 VCC BST PVCC 0.
PAGE 21
Data Sheet ADP1822 OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 13 1 12 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.
PAGE 22
ADP1822 Data Sheet NOTES Rev.
PAGE 23
Data Sheet ADP1822 NOTES Rev.