Datasheet
ADP1822 Data Sheet
Rev. D | Page 16 of 24
μA42−
=
LO
ONWC
LPK
OUT
HI
R
R
I
V
R
(14)
where:
I
PKFOLDBACK
is the desired short-circuit peak inductor current
limit.
I
LPK
is the peak inductor current limit during normal operation
and is also used in Equation 12.
05311-118
+
V
IN
M1
L V
OUT
C
OUT
M2
DH
DL
CSL
ADP1822
R
LO
R
HI
Figure 18. Short-Circuit Current Foldback Scheme
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. For the low-side resistor of the voltage
divider, R
BOT
, use 10 kΩ. A larger value resistor can be used but
results in a reduction in output voltage accuracy. Choose R
TOP
to
set the output voltage by
−
=
FB
FB
OUT
BOTTOP
V
VV
RR
(15)
where:
R
TOP
is the high-side voltage divider resistance.
R
BOT
is the low-side voltage divider resistance.
V
OUT
is the regulated output voltage.
V
FB
is the feedback regulation threshold, 0.6 V.
SETTING THE VOLTAGE MARGIN
The output voltage is margined by connecting a resistor from
FB to GND (for the high margin voltage) or FB to the output
voltage (for low margin voltage). The switches for margining
are supplied inside the ADP1822 and are controlled by the
MAR and MSEL inputs (see Table 1).
Choose the high margin resistor by
( )( )
MUP
BOTTOP
BOTTOP
UP
K
RR
RR
R
+
=
(16)
where:
R
UP
is the up-margin resistor from MUP to GND.
R
BOT
is the bottom voltage divider resistor from FB to GND.
R
TOP
is the top voltage divider resistor from FB to the output
voltage.
K
MUP
is the high voltage margin as a ratio of the output voltage
(for example, margining 4% up would be K
MUP
= 0.04).
Choose the low margin resistor by the equation
−−
=
MDN
OUT
FB
MDN
TOP
DN
K
V
V
K
R
R 1
(17)
where:
R
DN
is the down-margin resistor.
R
TOP
is the top voltage divider resistor from FB to the output
voltage.
V
FB
is the 0.6 V feedback voltage.
V
OUT
is the nominal output voltage setting.
K
MDN
is the down-margin as a ratio of the nominal output voltage
(for example, margining 4% down would be K
MDN
= 0.04).
For example, for an output voltage of 1.0 V and a ±5% margin,
choose
R
BOT
= 10 kΩ (18)
Thus,
kΩ67.6=
−
=
FB
FB
OUT
BOTTOP
V
VV
RR
(19)
and
( )( )
kΩ
K
RR
RR
R
MUP
BOTTOP
BOTTOP
UP
80=
+
=
(20)
and
kΩK
V
V
K
R
R
MDN
OUT
FB
MDN
TOP
DN
7.461 =
−−
=
(21)
COMPENSATING THE REGULATOR
The output of the error amplifier at COMP is used to compensate
the regulation control system. Connect a resistor capacitor (RC)
network from COMP to FB to compensate the regulator.
The first step of selecting the compensation components is
determining the desired regulation-control crossover frequency,
f
CO
. Choose a crossover frequency approximately 1/10 of the
switching frequency, or
10
SW
CO
f
f =
(22)
The characteristics of the output capacitor affect the compensation
required to stabilize the regulator. The output capacitor acts
with its ESR to form a zero. Calculate the ESR zero frequency by
( )
( )
ESRC
f
OUT
ESRZ
π2
1
=
(23)
Note that as similar capacitors are placed in parallel, the ESR
zero frequency remains the same.
If f
ESRZ
≤ f
CO
/2, use the ESR zero to stabilize the regulator (see the
Compensation Using the ESR Zero section). If f
ESRZ
≥ 2f
CO
, use a
feed-forward network to stabilize the regulator (see the
Compensation Using Feed-Forward section). If f
CO
/2 < f
ESRZ
< 2f
CO
,