Datasheet

EVAL-ADP1828LC
Rev. 0 | Page 3 of 12
COMPONENT DESIGN
For information about selecting power components and
calculating component values, see the ADP1828 data sheet.
INPUT CAPACITOR
Ceramic capacitors have very low ESR (in the order of 1 mΩ or
2 mΩ) and have large ripple current rating. For a 5 A output
with a V
IN
of 6 V to13.2 V and a V
OUT
of 1.8 V, three 22 µF
ceramic capacitors (22 µF/16 V/X5R/1210) are adequate.
INDUCTOR SELECTION
For this design, a 1.8 µH inductor (FDV0630-1R8M from Toko
Inc.) is selected. This is a compact, low-cost inductor with an
iron powder core, which generally has more core power loss but
at a lower cost than the ones with ferrite cores.
OUTPUT CAPACITOR SELECTION
The output voltage ripple can be approximated as follows:
2
2
2
)4(
8
1
ESLf
Cf
ESRIV
SW
OUT
SW
L
OUT
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+Δ=Δ
(1)
where:
ΔV
OUT
is the output ripple voltage.
ΔI
L
is the inductor ripple current.
ESR is the equivalent series resistance of the output capacitor.
ESL is the equivalent series inductance of the output capacitor.
A minimum capacitance at the output is needed to achieve a
fast load-step response and a reasonable overshoot voltage. The
minimum capacitance can be calculated as
up
UT
O
LOAD
OUT,min1
VV
LI
C
Δ
Δ
=
2
2
(2)
down
UTO
IN
LOAD
OUT,min2
VVV
LI
C
Δ−
Δ
=
)(2
2
(3)
where:
I
LOAD
is the step load.
V
up
is the output voltage overshoot when the load is
stepped down.
V
down
is the output voltage overshoot when the load is
stepped up.
V
IN
is the input voltage.
C
OUT,min1
is the minimum capacitance according to the overshoot
voltage V
up
.
C
OUT,min2
is the minimum capacitance according to the overshoot
voltage V
down
.
Select an output capacitance that is greater than both C
OUT, min1
and C
OUT, min2
.
In this design, multilayer ceramic capacitors (MLCCs) are used.
Because MLCCs have very low ESR and ESL, the output ripple
is dominated by the bulk capacitance. Two output ceramic
capacitors (100 µF/6.3 V/X5R/1210 and 47 µF/6.3 V/X5R/1206)
have been selected to satisfy a 5 A step load. Keep in mind that
the effective capacitance of the ceramic capacitor decreases as
the bias voltage increases.
MOSFET SELECTION
In general, select the high-side MOSFET with fast rise and fall
times and low input capacitance. Fast rise and fall times and low
input capacitance are especially important for circuits with low
duty cycles because switching loss is high. Select the low-side
MOSFET with low R
DSON
. Switching speed is not critical because
there is no switching loss in the low-side MOSFET. A small amount
of power is lost in the body diode of the low-side MOSFET during
the dead time.
For this evaluation board, a dual FET in a PowerPAK® SO-8
(Si7958DP from Vishay) has been selected. The PowerPAK SO-8
has a low thermal resistance, θ
JA
, and is adequate for handling
a 5 A output. An alternative is to use two single MOSFETs in
standard SO-8 packages. Furthermore, for an output current
less than 3 A, a dual FET in a standard SO-8 package is usually
adequate.
SOFT START
The soft start period is given by the following equation:
SSSS
tC
×
=
015.8
(4)
where:
C
SS
is the soft start capacitance in microfarads.
t
SS
is the soft start period in seconds.
A C
SS
of 150 nF, which yields a 19 ms soft start period, is chosen
for this design.
CURRENT LIMIT
The external current-limit resistor can be calculated by the
following equation:
A42
mV38
2
−
⎟
⎠
⎞
⎜
⎝
⎛
Δ
+
=
DSON
L
LIMIT
CL
R
I
I
R
(5)
where:
I
LIMIT
is the output limit current.
∆I
L
is the ripple current in the inductor.
R
DSON
is the on resistance of the low-side MOSFET.
−38 mV is the CSL threshold voltage.
∆I
L
can be approximated by
Lf
DV
I
SW
OUT
L
×
−
=Δ
)1(
(6)
where:
D is the duty cycle.
L is the inductance of the inductor.
In this design, R
DSON
of the MOSFET Si7958DP is 20 mΩ with a
VGS of 4.5 V. Because L is chosen to be 1.8 µH, ∆I
L
is calculated
to be 1.4 A. If I
LIMIT
is set to 6.5 A, RCL is calculated to be 2.88 kΩ.
A standard value of 2.87 kΩ is chosen. Keep in mind that R
DSON