Datasheet

EVAL-ADP1828LC
Rev. 0 | Page 4 of 12
of the MOSFET can vary by more than 25% from part to part,
and by more than 50% over the temperature range; therefore,
the actual current limit can vary by more than 50% from part to
part over the temperature range. For more information on this
topic, see the ADP1828 data sheet.
SWITCHING NOISE AND OVERSHOOT REDUCTION
An RC snubber can be added between SW and PGND to reduce
noise and ringing at the SW node and at the drains of the external
MOSFETs. In this design, an RC snubber is added with an R
SNUB
of 3.01 Ω and a C
SNUB
of 1.2 nF. Gate resistors can be added to
reduce overshoot voltage at the drains of the MOSFETs. For
more information, see the ADP1828 data sheet.
COMPENSATION DESIGN
Type III compensation is used in this design because all output
capacitors all ceramic with very low ESR. For information on
calculating the compensation component values, refer to the
ADP1828 data sheet.
C
HF
C
I
R
Z
C
FF
R
TOP
R
BOT
V
OUT
INTERNAL
VREF
FB
EA
COMP
R
FF
06906-002
Figure 2. Type III Compensation
The compensation values for this evaluation board have been
optimized as follows:
R
FF
= 422 Ω
C
FF
= 1 nF
R
Z
= 7.5 kΩ
C
I
= 3.9 nF
C
HF
= 33 pF
R
TOP
= 20 kΩ
R
BOT
= 10 kΩ