Datasheet

EVAL-ADP1829
Rev. 0 | Page 6 of 16
The compensation network consists of the error amplifier and
the impedance networks Z1 and Z2.
Figure 3 shows a Type III
compensation circuit. It provides two poles and two zeros. The
transfer function of this compensator is
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
π
+×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
π
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
π
+×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
π
+
×
−
=
P21P
Z2Z1
2
1
2
1
2
2
1
2
1
)(
f
s
f
s
ff
s
s
A
sG
EA
EA
(14)
where:
221
)(
1
RCC
A
EA
×+
=
24
2
1
CR
f
Z1
π
=
332
Z2
)(2
1
CRR
f
×+π
=
33
2
1
CR
f
1P
π
=
21
21
4
P2
2
1
CC
CC
R
f
+
×π
=
The loop gain can be written as
Ramp
EA
vd
V
sGsG
sT
)()(
)(
×
=
(15)
where V
Ramp
is the PWM ramp peak voltage; in the ADP1829,
V
Ramp
= 1.3 V.
Use the following guidelines to select the compensation
components:
1.
Set the loop gain cross frequency f
C
. A good choice is to
place the cross frequency f
C
at f
s
/10 for fast response.
2.
Cancel ESR zero f
Z
by compensator pole f
P1
.
3.
Place the high frequency pole f
P2
to achieve maximum
attenuation of switching ripple and high frequency noise. A
good choice is f
P2
= (5 ~ 10) f
C
.
4.
Place two compensator zeros near the power stage resonant
frequency f
O
. In general, place f
Z1
below f
O
and place f
Z2
between f
O
and f
C
.
5.
Check the phase margin to obtain good regulation
performance.