Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - voltage regulators - DC DC switch controllers LFCSP 10 WD

Synchronous Buck Controller with

Constant On-Time and Valley Current Mode

Data Sheet

ADP1870/ADP1871

Rev. B

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FEATURES

Power input voltage range: 2.95 V to 20 V

On-board bias regulator

Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 kHz, and 1.0 MHz options

No current-sense resistor required

Power saving mode (PSM) for light loads (ADP1871 only)

Resistor-programmable current-sense gain

Thermal overload protection

Short-circuit protection

Precision enable input

Integrated bootstrap diode for high-side drive

Starts into a precharged load

Small, 10-lead MSOP and LFCSP packages

APPLICATIONS

Telecom and networking systems

Mid to high end servers

Set-top boxes

DSP core power supplies

12 V input POL supplies

GENERAL DESCRIPTION

The ADP1870/ADP1871 are versatile current-mode, synchronous

step-down controllers that provide superior transient response,

optimal stability, and current-limit protection by using a constant

on-time, pseudo-fixed frequency with a programmable current-

limit, current-control scheme. In addition, these devices offer

optimum performance at low duty cycles by utilizing valley

current-mode control architecture. This allows the ADP1870/

ADP1871 to drive all N-channel power stages to regulate output

voltages as low as 0.6 V.

The ADP1871 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the Power Saving Mode (PSM) Version (ADP1871)

section for more information).

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1870/ADP1871 are well

suited for a wide range of applications that require a single-input

power supply range from 2.95 V to 20 V. Low voltage biasing is

supplied via a 5 V internal LDO.

TYPICAL APPLICATIONS CIRCUIT

COMP/EN BST

FB DRVH

GND

VREG DRVL

PGND

VIN

VREG

VREG2

BOT

TOP

OUT

RES

OUT

BST

LOAD

= 2.95V TO 20V

ADP1870/

ADP1871

08730-001

Figure 1.

100

10 100 1k

10k 100k

EFFICIENCY (%)

LOAD CURRENT (mA)

= 25°C

OUT

= 1.8V

= 300kHz

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

= 5V (PSM)

= 13V (PSM)

= 16.5V (PSM)

= 13V

= 16.5V

08730-102

Figure 2. Efficiency vs. Load Current (V

OUT

= 1.8 V, 300 kHz)

In addition, an internally fixed soft start period is included to limit

input in-rush current from the input supply during startup and

to provide reverse current protection during soft start for a pre-

charged output. The low-side current-sense, current-gain scheme

and integration of a boost diode, along with the PSM/forced pulse-

width modulation (PWM) option, reduce the external part count

and improve efficiency.

The ADP1870/ADP1871 operate over the −40°C to +125°C

junction temperature range and are available in a 10-lead MSOP

and LFCSP packages.

Summary of content (44 pages)

PAGE 1
FEATURES TYPICAL APPLICATIONS CIRCUIT VIN = 2.95V TO 20V VIN CC VOUT RTOP RC ADP1870/ ADP1871 CC2 COMP/EN BST CBST FB GND CVREG2 COUT Q2 SW VREG DRVL PGND RRES LOAD 100 VIN = 5V (PSM) 95 90 75 EFFICIENCY (%) 80 VIN = 16.5V 70 65 VIN = 13V 60 VIN = 13V (PSM) 55 50 45 40 VIN = 16.5V (PSM) Available in three frequency options (300 kHz, 600 kHz, and 1.
PAGE 2
ADP1870/ADP1871 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Saving Mode (PSM) Version (ADP1871).................... 22 Applications ....................................................................................... 1 Timer Operation ........................................................................ 22 General Description .........................................................................
PAGE 3
Data Sheet ADP1870/ADP1871 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, VBST − VSW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
PAGE 4
ADP1870/ADP1871 Parameter ADP1870ARMZ-0.6/ ADP1871ARMZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1870ARMZ-1.0/ ADP1871ARMZ-1.0 (1.
PAGE 5
Data Sheet ADP1870/ADP1871 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VREG to PGND, GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND θJA (10-Lead MSOP) 2-Layer Board 4-Layer Board θJA (10-Lead LFCSP) 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) THERMAL RESISTANCE Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VREG + 0.3 V) −0.3 V to (VREG + 0.3 V) −2.
PAGE 6
ADP1870/ADP1871 Data Sheet VIN 1 FB 3 ADP1870/ ADP1871 GND 4 TOP VIEW (Not to Scale) COMP/EN 2 VREG 5 10 BST 9 SW 8 DRVH 7 PGND 6 DRVL NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 08730-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VIN COMP/EN FB GND 5 VREG 6 DRVL 7 8 9 10 PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
PAGE 7
Data Sheet ADP1870/ADP1871 VIN = 16.5V VIN = 13V TA = 25°C VOUT = 0.8V fSW = 300kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100k EFFICIENCY (%) 08730-105 EFFICIENCY (%) LOAD CURRENT (mA) EFFICIENCY (%) VIN = 16.5V TA = 25°C VOUT = 7V fSW = 300kHz WÜRTH INDUCTOR: 7443551200, L = 2.0µH, DCR = 2.
PAGE 8
100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100 Data Sheet 0.807 0.806 VIN = 13V 0.805 VIN = 16.5V TA = 25°C VOUT = 0.8V fSW = 1.0MHz 10k 100k LOAD CURRENT (mA) 0.798 0.797 0.796 0.792 VIN = 13V +125°C +25°C –40°C 0 2000 VIN = 16.5V +125°C +25°C –40°C 4000 6000 8000 10,000 LOAD CURRENT (mA) 1.821 VIN = 13V VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303022, L = 0.22µH, DCR = 0.
PAGE 9
Data Sheet ADP1870/ADP1871 0.808 0.807 0.805 0.806 0.803 OUTPUT VOLTAGE (V) FREQUENCY (kHz) 0.804 0.802 0.800 0.798 0.801 0.799 0.797 0.795 0.793 0.796 0.791 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 0.787 0 6000 8000 10,000 Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V OUTPUT VOLTAGE (V) 1.815 1500 3000 4500 VIN = 16.5V +125°C +25°C –40°C 6000 7500 9000 1.810 1.805 1.800 VIN = 13V +125°C +25°C –40°C 1.
PAGE 10
ADP1870/ADP1871 Data Sheet 601.0 900 SWITCHING FREQUENCY (kHz) 600.0 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 597.5 840 820 800 780 760 740 25.0 57.5 90.0 700 13.0 08730-121 –7.5 122.5 TEMPERATURE (°C) +125°C +25°C –40°C 315 14.0 14.5 15.0 15.5 16.0 16.5 VIN (V) Figure 22. Feedback Voltage vs. Temperature 325 13.5 08730-124 720 597.0 –40.0 Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V 280 NO LOAD VIN = 13V VIN = 20V VIN = 16.
PAGE 11
Data Sheet VIN = 13V VIN = 16.5V 334 +125°C +25°C –40°C 326 FREQUENCY (kHz) FREQUENCY (kHz) 330 322 318 314 310 306 298 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) 08730-027 302 510 +125°C +25°C –40°C 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V 850 +125°C +25°C –40°C VIN = 13V VIN = 16.5V VIN = 13V VIN = 16.5V 0 Figure 28. Frequency vs.
PAGE 12
ADP1870/ADP1871 Data Sheet 1450 82 VIN = 13V VIN = 16.5V 1400 +125°C +25°C –40°C MAXIMUM DUTY CYCLE (%) 1300 1250 1200 1150 1100 78 76 74 72 70 68 66 1050 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) 62 5.5 08730-033 0 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 VIN (V) Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN) 680 2.657 630 2.656 580 MINUMUM OFF-TIME (ns) 2.658 2.655 2.654 2.653 2.
PAGE 13
Data Sheet 80 +125°C +25°C –40°C RECTIFIER DROP (mV) 640 560 480 400 320 240 80 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1200 1120 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz 48 40 32 24 16 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 43. Lower-Side MOSFET Body Diode Conduction Time vs. VREG TA = 25°C OUTPUT VOLTAGE 1 1040 RECTIFIER DROP (mV) 56 8 2.7 Figure 40. Internal Rectifier Drop vs.
PAGE 14
ADP1870/ADP1871 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 SW NODE 1 3 SW NODE LOW SIDE 3 CH4 100mV B W M400ns T 30.6% A CH3 2.20V CH1 10A Ω CH3 20V CH2 200mV CH4 5V B W M20µs T 48.2% A CH1 3.40A 08730-048 CH1 5A Ω CH3 10V 08730-045 4 Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled, 12 A (See Figure 94 Application Circuit) Figure 46.
PAGE 15
Data Sheet ADP1870/ADP1871 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 INDUCTOR CURRENT 12A NEGATIVE STEP 2 1 SW NODE LOW SIDE 4 3 SW NODE LOW SIDE CH2 200mV CH4 5V B W M10µs T 23.8% A CH1 5.60A CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A (See Figure 94 Application Circuit) M2ms T 32.8% A CH1 720mV 08730-054 CH1 10A Ω CH3 20V 3 08730-051 4 Figure 55.
PAGE 16
ADP1870/ADP1871 Data Sheet 18ns (tr,DRVL ) LOW SIDE OUTPUT VOLTAGE 1 4 24ns (tpdh,DRVL ) HIGH SIDE LOW SIDE 4 HS MINUS SW SW NODE 11ns (tf,DRVH ) SW NODE 3 2 3 M INDUCTOR CURRENT CH2 5A Ω CH4 2V M1ms T 63.2% A CH1 1.56V 08730-057 CH1 1V BW CH3 10V BW CH2 5V CH3 5V CH4 2V MATH 2V 20ns Figure 58. Soft Start and RES Detect Waveform A CH2 4.20V Figure 61. Upper-Side Driver Falling and Lower-Side Rising Edge Waveforms (CIN = 4.3 nF (Upper-/Lower-Side MOSFET), QTOTAL = 27 nC (VGS = 4.
PAGE 17
Data Sheet ADP1870/ADP1871 1.30 1.25 1.15 +125°C 1.10 1.05 +25°C 1.00 0.95 –40°C 0.90 0.85 0.80 0.75 0.70 2.7 3.1 3.5 3.9 4.3 4.7 VREG (V) 5.1 5.5 08730-163 QUIESCENT CURRENT (mA) 1.20 Figure 64. Quiescent Current vs. VREG Rev.
PAGE 18
ADP1870/ADP1871 Data Sheet ADP1870/ADP1871 BLOCK DIAGRAM ADP1870/ADP1871 VREG tON TIMER VIN C PRECISION ENABLE BLOCK TO ENABLE ALL BLOCKS I SW INFORMATION LDO VREG R (TRIMMED) tON = 2RC(VOUT/VIN) REF SW FILTER VREG BST BIAS BLOCK AND REFERENCE STATE MACHINE REF_ZERO TON BG_REF DH_LO PSM IN_SS DRVH ISS SS COMP PSM CSS DRVL VREG LS DRVL DL_LO PGND PWM 800kΩ IREV COMP LOWER COMP CLAMP SW 8kΩ PWM IREV 0.
PAGE 19
Data Sheet ADP1870/ADP1871 THEORY OF OPERATION ADP1870/ADP1871, reducing the supply current of the devices to approximately 140 µA. For more information, see Figure 67. ADP1870/ADP1871 FB VREG SS COMP/EN STARTUP CC The ADP1870/ADP1871 have an internal regulator (VREG) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VREG (Pin 5) and PGND (Pin 7) pins.
PAGE 20
ADP1870/ADP1871 Data Sheet VIN and VREG be tied together if the VIN pin is subjected to a 2.75 V rail. SW CS AMP PGND Table 5. Power Input and LDO Output Configurations VREG Float Connect to VIN <5.5 V Ranges above and below 5.5 V Float Float Comments Must use the LDO LDO drop voltage is not realized (that is, if VIN = 2.75 V, then VREG = 2.75 V) LDO drop is realized LDO drop is realized, minimum VIN recommendation is 2.95 V CS GAIN SET ADC 0.4V DRVL 08730-067 VIN >5.5 V <5.
PAGE 21
Data Sheet ADP1870/ADP1871 I CLIM  1.4 V ACS  RON where: RON is the channel impedance of the lower-side MOSFET. ACS is the current-sense gain multiplier (see Table 6 and Table 7). Although the ADP1870/ADP1871 have only four discrete currentsense gain settings for a given RON variable, Table 7 and Figure 71 outline several available options for the valley current setpoint based on various RON values. The valley current limit is programmed as outlined in Table 7 and Figure 71.
PAGE 22
ADP1870/ADP1871 Data Sheet SYNCHRONOUS RECTIFIER The ADP1870/ADP1871 employ an internal lower-side MOSFET driver to drive the external upper- and lower-side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency, but also ensures proper charging to the bootstrap capacitor located at the upper-side driver input.
PAGE 23
Data Sheet ADP1870/ADP1871 VREG tON VIN To illustrate this feature more clearly, this section describes one such load transient event—a positive load step—in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (DRVL on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. C I R (TRIMMED) 08730-075 SW INFORMATION Figure 77.
PAGE 24
ADP1870/ADP1871 Data Sheet APPLICATIONS INFORMATION Table 8. Recommended Inductors FEEDBACK RESISTOR DIVIDER INDUCTOR SELECTION L (µH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by OUTPUT RIPPLE VOLTAGE (ΔVRR) The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V.
PAGE 25
Data Sheet ADP1870/ADP1871 Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance might be lost due to derating as the voltage applied across the capacitor is increased (see Figure 80). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 µF.
PAGE 26
ADP1870/ADP1871 Data Sheet EFFICIENCY CONSIDERATIONS 800 One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power.
PAGE 27
Data Sheet ADP1870/ADP1871 Diode Conduction Loss The ADP1870/ADP1871 employ anticross conduction circuitry that prevents the upper- and lower-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage.
PAGE 28
ADP1870/ADP1871 Data Sheet 130 THERMAL CONSIDERATIONS Table 9 lists the thermal impedance for the ADP1870/ADP1871, which are available in both 10-lead MSOP and 10-lead LFCSP packages. Thermal Impedance 213.1°C/W 171.7°C/W 40°C/W 150 600kHz 300kHz 1MHz MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (°C) 130 VOUT = 0.8V VOUT = 1.8V VOUT = HIGH SETPOINT 120 110 110 105 100 95 90 85 80 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0 The maximum junction temperature allowed for the ADP1870/ ADP1871 ICs is 125°C.
PAGE 29
Data Sheet ADP1870/ADP1871 (4) PDISS ( LDO ) = PDR ( LOSS ) + (VIN − VREG ) × ( f SW × Ctotal × VREG + I BIAS ) where: PDISS(LDO) is the power dissipated through the pass device in the LDO block across VIN and VREG. Ctotal is the CGD + CGS of the external MOSFET. VREG is the LDO output voltage and bias voltage. VIN is the high voltage input. IBIAS is the dc input bias current. PDR(LOSS) is the MOSFET driver loss. For example, if the external MOSFET characteristics are θJA (10-lead MSOP) = 171.
PAGE 30
ADP1870/ADP1871 Data Sheet Therefore, an appropriate inductor selection is five 270 µF polymer capacitors with a combined ESR of 3.5 mΩ. C COMP = = ((VOUT 1× 10 −6 = (L × I 2 LOAD ) − ∆VOVSHT ) 2 − (VOUT )2 ) × (15 A) Loss Calculations Duty cycle = 1.8/12 V = 0.15 2 2 (1.8 − 45 mV) − (1.8) 2πRCOMP f ZERO 1 2 × 3.14 × 100 × 103 × 6.25 × 103 = 250 pF Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate: C OUT = 1 RON (N2) = 5.
PAGE 31
Data Sheet ADP1870/ADP1871 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 15 kΩ, RON = 5.4 mΩ (BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A. The ADP1871 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Marking Code SAP Model ADP1870ARMZ-0.3-R7/ ADP1871ARMZ-0.3-R7 ADP1870ARMZ-0.6-R7/ ADP1871ARMZ-0.6-R7 ADP1870ARMZ-1.
PAGE 32
ADP1870/ADP1871 Data Sheet Marking Code SAP Model ADP1870 LDY LDY ADP1871 LDN LDN VOUT (V) 5 7 VIN (V) 16.5 16.5 CIN (µF) 3 × 109 3 × 109 COUT (µF) 3 × 476 222 + 476 L1 (µH) 1.0 1.0 RC (kΩ) 34 34 CCOMP (pF) 268 228 CPAR (pF) 27 23 See the Inductor Selection section and Table 11. 22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 3 560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm). 4 270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.
PAGE 33
Data Sheet ADP1870/ADP1871 LAYOUT CONSIDERATIONS Figure 85 shows the schematic of a typical ADP1870/ADP1871 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.
PAGE 34
ADP1870/ADP1871 Data Sheet SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC.
PAGE 35
ADP1870/ADP1871 08730-084 Data Sheet Figure 87. Layer 2 of Evaluation Board Rev.
PAGE 36
ADP1870/ADP1871 Data Sheet TOP RESISTOR FEEDBACK TAP 08730-083 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 86 TO FIGURE 88). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 88, LAYER 4 FOR PGND TAP). Figure 88. Layer 3 of Evaluation Board Rev.
PAGE 37
Data Sheet ADP1870/ADP1871 BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE 08730-085 PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. Figure 89. Layer 4 (Bottom Layer) of Evaluation Board IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND).
PAGE 38
ADP1870/ADP1871 Data Sheet (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D. SW LAYER 1: SENSE LINE FOR SW (DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND (SOURCE OF LOWER MOSFET) 08730-087 VOUT VIN PGND 08730-086 Figure 91. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2) Figure 90.
PAGE 39
Data Sheet ADP1870/ADP1871 TYPICAL APPLICATIONS CIRCUITS 15 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 12V JP3 C28 10µF CC 571pF RC 47kΩ CF 57pF VOUT R1 30kΩ R2 15kΩ C2 0.1µF ADP1870/ ADP1871 BST 10 1 VIN 2 COMP/EN 3 FB DRVH 8 4 GND PGND 7 5 VREG DRVL 6 C12 100nF Q1 C6 22µF 1.0µH R4 0Ω Q3 C7 22µF C9 N/A C8 N/A Q2 SW 9 C1 1µF C5 22µF C4 22µF C3 22µF Q4 VOUT = 1.8V, 15A C20 270µF R6 2Ω C13 1.
PAGE 40
ADP1870/ADP1871 Data Sheet 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 13V JP3 C28 10µF CF 53pF VOUT R1 30kΩ C2 0.1µF R2 15kΩ C1 1µF ADP1870/ ADP1871 1 VIN 2 COMP/EN 3 FB DRVH 8 4 GND PGND 7 5 VREG DRVL 6 BST 10 C12 100nF C3 22µF Q1 C4 22µF C5 22µF C6 N/A 1.4µH Q3 C8 N/A C9 270µF Q2 SW 9 R4 0Ω C7 N/A Q4 R6 2Ω C13 1.5nF VOUT = 1.
PAGE 41
Data Sheet ADP1870/ADP1871 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 95. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 10 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 1.74 1.64 1.
PAGE 42
ADP1870/ADP1871 Data Sheet ORDERING GUIDE Model 1 ADP1870ARMZ-0.3-R7 ADP1870ARMZ-0.6-R7 ADP1870ARMZ-1.0-R7 ADP1871ARMZ-0.3-R7 ADP1871ARMZ-0.6-R7 ADP1871ARMZ-1.0-R7 ADP1870ACPZ-0.3-R7 ADP1870ACPZ-0.6-R7 ADP1870ACPZ-1.0-R7 ADP1871ACPZ-0.3-R7 ADP1871ACPZ-0.6-R7 ADP1871ACPZ-1.0-R7 ADP1870-0.3-EVALZ ADP1870-0.6-EVALZ ADP1870-1.0-EVALZ ADP1871-0.3-EVALZ ADP1871-0.6-EVALZ ADP1871-1.
PAGE 43
Data Sheet ADP1870/ADP1871 NOTES Rev.