Datasheet

Data Sheet ADP1870/ADP1871
Rev. B | Page 27 of 44
Diode Conduction Loss
The ADP1870/ADP1871 employ anticross conduction circuitry
that prevents the upper- and lower-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode. The amount of loss through the
body diode of the lower-side MOSFET during the antioverlap
state is given by the following expression:
2
)(
)(

F
LOAD
SW
LOSSBODY
LOSSBODY
VI
t
t
P
where:
t
BODY(LOSS)
is the body conduction time (refer to Figure 82 for
dead time periods).
t
SW
is the period per switching cycle.
V
F
is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the V
F
parameter.)
80
72
64
56
48
40
32
24
16
8
2.7 5.54.84.13.4
BODY DIODE CONDUCTION TIME (ns)
V
REG
(V)
+125°C
+25°C
–40°C
1MHz
300kHz
08730-080
Figure 82. Body Diode Conduction Time vs. Low Voltage Input (V
REG
)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered
iron inductors have higher core losses. It is recommended that
shielded ferrite core material type inductors be used with the
ADP1870/ADP1871 for a high current, dc-to-dc switching
application to achieve minimal loss and negligible electromagnetic
interference (EMI).
2
)(
LOAD
LOSSDCR
IDCRP 
+ Core Loss
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their
physical geometries, is their large equivalent series resistance
(ESR) and large equivalent series inductance (ESL). Aluminum
electrolytic capacitors have such high ESR that they cause
undesired input voltage ripple magnitudes and are generally not
effective at high switching frequencies.
If bulk capacitors are to be used, it is recommended that muli-
layered ceramic capacitors (MLCC) be used in parallel due to
their low ESR values. This dramatically reduces the input voltage
ripple amplitude as long as the MLCCs are mounted directly
across the drain of the upper-side MOSFET and the source
terminal of the lower-side MOSFET (see the Layout
Considerations section). Improper placement and mounting of
these MLCCs may cancel their effectiveness due to stray
inductance and an increase in trace impedance.

OUT
OUT
IN
OUT
LOAD,maxrmsCIN
V
VVV
II


,
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
V
RIPPLE,max
= V
RIPP
+ (I
LOAD,max
× ESR)
where:
V
RIPP
is usually 1% of the minimum voltage input.
I
LOAD,max
is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
Inserting V
RIPPLE,max
into the charge balance equation to calculate
the minimum input capacitor requirement gives
SW
RIPPLE,max
LOAD,max
IN,min
f
DD
V
I
C
)1( 

or
RIPPLE,max
SW
LOAD,max
IN,min
Vf
I
C
4

where D = 50%.