Datasheet

Data Sheet ADP1870/ADP1871
Rev. B | Page 29 of 44
)()(
)()( BIASREGtotalSWREGINLOSSDRLDODISS
IVCfVVPP +×××−+=
(4)
where:
P
DISS(LDO)
is the power dissipated through the pass device in the
LDO block across VIN and VREG.
C
total
is the C
GD
+ C
GS
of the external MOSFET.
V
REG
is the LDO output voltage and bias voltage.
V
IN
is the high voltage input.
I
BIAS
is the dc input bias current.
P
DR(LOSS)
is the MOSFET driver loss.
For example, if the external MOSFET characteristics are θ
JA
(10-lead MSOP) = 171.2°C/W, f
SW
= 300 kHz, I
BIAS
= 2 mA,
C
upperFET
= 3.3 nF, C
lowerFET
= 3.3 nF, V
DR
= 4.62 V, a n d V
REG
= 5.0 V,
then the power loss is
( )
[ ]
( )
[ ]
))002.00.5103.310300(0.5(
))002.062.4103.310300(62.4(
93
93
)(
+×××××+
+×××××=
+×+
+×=
−
−
BIASREG
lowerFET
SWREG
BIAS
DR
upperFET
SW
DR
LOSSDR
IVCfV
IVCfVP
= 57.12 mW
)002.05103.310300()V5V13(
)()(
93
)(
+×××××−=
+×××−=
−
BIASREG
total
SWREG
IN
LDODISS
IVCfVVP
= 55.6 mW
mW6.55mW13.77
)()()(
+=
+=
LOSSDRLDODISSTOTALDISS
PPP
= 132.73 mW
The rise in package temperature (for 10-lead MSOP) is
mW05.132°C2.171
)(
×=
×θ=
LOSSDR
JA
R
PT
= 22.7°C
Assuming a maximum ambient temperature environment of 85°C,
°C72.107°C85°C7.22
=+=×=
A
RJ
TTT
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1870/ADP1871 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V
OUT
= 1.8 V, I
LOAD
= 15 A (pulsing),
V
IN
= 12 V (typical), and f
SW
= 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
V
RIPP
= 120 mV
V
MAX,RIPPLE
= V
RIPP
− (I
LOAD,MAX
× ESR)
= 120 mV − (15 A × 0.001) = 45 mV
mV105103004
A15
4
3
,
,
×××
==
RIPPLEMAXSW
MAXLOAD
IN,min
Vf
I
C
= 120 µF
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
I
RMS
= I
LOAD
/2 = 7.5 A
P
CIN
= (I
RMS
)
2
× ESR = (7.5 A)
2
× 1 mΩ = 56.25 mW
Inductor
Determine inductor ripple current amplitude as follows:
3
LOAD
L
I
I ≈∆
= 5 A
so calculating for the inductor value
V2.13
V8.1
10300V5
)V8.1V2.13(
)(
3
×
××
−
=
×
×∆
−
=
IN,MAX
OUT
SW
L
OUT
IN,MAX
V
V
fI
VV
L
= 1.03 µH
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 8
with peak current handling of 20 A.
2
)(
L
LOSSDCR
IDCRP ×=
= 0.003 × (15 A)
2
= 675 mW
Current Limit Programming
The valley current is approximately
15 A − (5 A × 0.5) = 12.5 A
Assuming a lower-side MOSFET R
ON
of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an A
CS
of 24 V / V.
Choose a programmable resistor of R
RES
= 100 kΩ for a current-
sense gain of 24 V / V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady state
operating point. In this case, the ADP1870’s advantage is that
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
ΔV
DROOP
= 0.05 × 1.8 V = 90 mV
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
)mV90(10300
A15
2
)(
2
3
××
×=
∆×
∆
×=
DROOPSW
LOAD
OUT
Vf
I
C
= 1.11 mF