Datasheet

Data Sheet ADP1870/ADP1871
Rev. B | Page 33 of 44
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on
how the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components is essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.
Figure 85 shows the schematic of a typical ADP1870/ADP1871
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and V
OUT
traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1µH, 3.3mΩ, 20A 7443552100
R5
100kΩ
Q3
Q4
Q1
Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C12
100nF
V
OUT
= 1.8V, 15A
C3
22µF
C4
22µF
C5
22µF
C6
22µF
C7
22µF
C8
N/A
C9
N/A
C23
270µF
+
C22
270µF
+
C21
270µF
+
C20
270µF
+
C27
N/A
C14 TO C19
N/A
+
C26
N/A
+
C25
N/A
+
C24
N/A
+
1.0µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
R4
0Ω
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VREG
6
DRVL
ADP1870/
ADP1871
C
C
571pF
C
F
57pF
R
C
47kΩ
C1
1µF
C28
10µF
C2
0.1µF
JP3
08730-081
Figure 85. ADP1870 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)