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Synchronous Buck Controller with Constant

On-Time and Valley Current Mode

Data Sheet

ADP1874/ADP1875

Rev. A

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FEATURES

Power input voltage range: 2.95 V to 20 V

On-board bias regulator

Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 kHz, and 1.0 MHz options

No current-sense resistor required

Power saving mode (PSM) for light loads (ADP1875 only)

Resistor programmable current limit

Power good with internal pull-up resistor

Externally programmable soft start

Thermal overload protection

Short-circuit protection

Standalone precision enable input

Integrated bootstrap diode for high-side drive

Starts into a precharged output

Available in a 16-lead QSOP package

APPLICATIONS

Telecom and networking systems

Mid- to high-end servers

Set-top boxes

DSP core power supplies

GENERAL DESCRIPTION

The ADP1874/ADP1875 are versatile current mode, synchronous

step-down controllers. They provide superior transient response,

optimal stability, and current-limit protection by using a constant

on-time, pseudo fixed frequency with a programmable current

limit, current control scheme. In addition, these devices offer

optimum performance at low duty cycles by using a valley, current

mode control architecture. This allows the ADP1874/ADP1875

to drive all N-channel power stages to regulate output voltages

to as low as 0.6 V.

The ADP1875 is the power saving mode (PSM) version of

the device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the ADP1875 Power Saving Mode (PSM) section for

more information).

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz, plus the PSM option), the ADP1874/ADP1875 are well

suited for a wide range of applications that require a single-input

power supply range from 2.95 V to 20 V. Low voltage biasing is

supplied via a 5 V internal low dropout regulator (LDO).

TYPICAL APPLICATIONS CIRCUIT

COMP

BST

DRVH

GND

VREG

VREG_IN

RES

DRVL

PGND

VIN

VREG

VREG2

BOT

TOP

OUT

10kΩ

VREG

OUT

BST

LOAD

= 2.95V TO 20V

ADP1874/

ADP1875

RES

TRK1

PGOOD

PGD

EXT

TRACK

TRK2

MASTER

09347-001

Figure 1. Typical Applications Circuit

100

10 100 1k

10k 100k

EFFICIENCY (%)

LOAD CURRENT (mA)

= 25°C

OUT

= 1.8V

= 300kHz

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8mΩ

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

= 5V (PSM)

= 13V (PSM)

= 16.5V (PSM)

= 13V

= 16.5V

09347-102

Figure 2. ADP1874/ADP1875 Efficiency vs. Load Current (V

OUT

= 1.8 V, 300 kHz)

In addition, soft start programmability is included to limit input

in-rush current from the input supply during startup and to

provide reverse current protection during precharged output

conditions. The low-side current sense, current gain scheme, and

integration of a boost diode, along with the PSM/forced pulse-

width modulation (PWM) option, reduce the external part count

and improve efficiency.

The ADP1874/ADP1875 operate over the −40°C to +125°C

junction temperature range and are available in a 16-lead QSOP

package.

Summary of content (44 pages)

PAGE 1
FEATURES TYPICAL APPLICATIONS CIRCUIT VIN = 2.95V TO 20V The ADP1874/ADP1875 are versatile current mode, synchronous step-down controllers. They provide superior transient response, optimal stability, and current-limit protection by using a constant on-time, pseudo fixed frequency with a programmable current limit, current control scheme. In addition, these devices offer optimum performance at low duty cycles by using a valley, current mode control architecture.
PAGE 2
ADP1874/ADP1875 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timer Operation ........................................................................ 23 Applications ....................................................................................... 1 Pseudo-Fixed Frequency ........................................................... 24 General Description ......................................................
PAGE 3
Data Sheet ADP1874/ADP1875 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
PAGE 4
ADP1874/ADP1875 Parameter ADP1874ARQZ-0.6/ ADP1875ARQZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1874ARQZ-1.0/ ADP1875ARQZ-1.0 (1.
PAGE 5
Data Sheet Parameter TRACKING Track Input Voltage Range FB-to-Tracking Offset Voltage Leakage Current ADP1874/ADP1875 Symbol Test Conditions/Comments Min Typ 0 0.5 V < TRACK < 0.6 V, offset = VFB − VTRACK VTRACK = 5 V 1 63 1 Max Unit 5 V mV nA 50 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the upper side and lower side MOSFETs being Infineon BSC042N03MS G. Guaranteed by design.
PAGE 6
ADP1874/ADP1875 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VREG, VREG_IN, TRACK to PGND, GND VIN, EN, PGOOD to PGND FB, COMP, RES, SS to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND PGOOD Input Current θJA (16-Lead QSOP) 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VREG + 0.3 V) −0.3 V to (VREG + 0.
PAGE 7
Data Sheet ADP1874/ADP1875 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 BST VIN 1 15 SW COMP 2 FB 4 GND 5 RES 6 VREG 7 VREG_IN 8 ADP1874/ ADP1875 14 DRVH 13 PGND TOP VIEW 12 DRVL (Not to Scale) 11 PGOOD 10 SS 9 TRACK 09347-003 EN 3 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic VIN COMP 3 4 5 EN FB GND 6 7 RES VREG 8 9 VREG_IN TRACK 10 SS 11 PGOOD 12 DRVL 13 14 15 16 PGND DRVH SW BST Description High-Side Input Voltage.
PAGE 8
ADP1874/ADP1875 Data Sheet VIN = 16.5V VIN = 13V TA = 25°C VOUT = 0.8V fSW = 300kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100k EFFICIENCY (%) 09347-105 EFFICIENCY (%) LOAD CURRENT (mA) EFFICIENCY (%) VIN = 16.5V TA = 25°C VOUT = 7V fSW = 300kHz WÜRTH INDUCTOR: 7443551200, L = 2.0µH, DCR = 2.
PAGE 9
ADP1874/ADP1875 100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100 0.807 0.806 VIN = 13V 0.805 VIN = 16.5V TA = 25°C VOUT = 0.8V fSW = 1.0MHz 10k 100k LOAD CURRENT (mA) 0.798 0.797 0.796 VIN = 16.5V +125°C +25°C –40°C VIN = 13V +125°C +25°C –40°C 0.792 0 2000 4000 6000 8000 10,000 LOAD CURRENT (mA) 1.821 VIN = 13V VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303022, L = 0.22µH, DCR = 0.
PAGE 10
ADP1874/ADP1875 Data Sheet 0.808 0.807 0.805 0.806 0.803 OUTPUT VOLTAGE (V) FREQUENCY (kHz) 0.804 0.802 0.800 0.798 0.801 0.799 0.797 0.795 0.793 0.796 0.791 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 0.787 0 4000 6000 8000 10,000 Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V 1.820 1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 1.778 1.776 1.774 1.772 1.
PAGE 11
Data Sheet ADP1874/ADP1875 601.0 900 SWITCHING FREQUENCY (kHz) 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 840 820 800 780 760 740 25.0 57.5 90.0 700 13.0 09347-121 –7.5 122.5 TEMPERATURE (°C) +125°C +25°C –40°C 315 14.0 14.5 15.0 15.5 16.0 16.5 VIN (V) Figure 22. Feedback Voltage vs. Temperature 325 13.5 09347-124 720 597.0 –40.0 Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V 280 NO LOAD VIN = 13V VIN = 20V VIN = 16.
PAGE 12
ADP1874/ADP1875 VIN = 13V VIN = 16.5V 334 +125°C +25°C –40°C 326 FREQUENCY (kHz) FREQUENCY (kHz) 330 322 318 314 310 306 298 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) 09347-027 302 740 733 726 719 712 705 698 691 684 677 670 663 656 649 642 635 628 621 0 Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V 850 +125°C +25°C –40°C VIN = 13V VIN = 16.5V 510 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 28.
PAGE 13
Data Sheet ADP1874/ADP1875 1450 82 VIN = 13V VIN = 16.5V 1400 +125°C +25°C –40°C MAXIMUM DUTY CYCLE (%) 1300 1250 1200 1150 1100 78 76 74 72 70 68 66 1050 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) 62 5.5 09347-033 1000 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 VIN (V) Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN) 680 2.657 630 2.656 580 MINUMUM OFF-TIME (ns) 2.658 2.655 2.654 2.
PAGE 14
ADP1874/ADP1875 80 +125°C +25°C –40°C RECTIFIER DROP (mV) 640 560 480 400 320 240 80 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1200 1120 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz 48 40 32 24 16 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 43. Lower Side MOSFET Body Diode Conduction Time vs. VREG TA = 25°C OUTPUT VOLTAGE 1 1040 RECTIFIER DROP (mV) 56 8 2.7 Figure 40. Internal Rectifier Drop vs.
PAGE 15
Data Sheet ADP1874/ADP1875 OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 SW NODE 1 3 SW NODE LOW SIDE 3 CH4 100mV B W M400ns T 30.6% A CH3 2.20V CH1 10A Ω CH3 20V CH2 200mV CH4 5V B W M20µs T 48.2% A CH1 3.40A 09347-048 CH1 5A Ω CH3 10V 09347-045 4 Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled, 12 A (See Figure 99 Application Circuit) Figure 46.
PAGE 16
ADP1874/ADP1875 Data Sheet OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 INDUCTOR CURRENT 12A NEGATIVE STEP 2 1 SW NODE LOW SIDE 4 3 SW NODE LOW SIDE CH2 200mV CH4 5V B W M10µs T 23.8% A CH1 5.60A CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A (See Figure 99 Application Circuit) M2ms T 32.8% A CH1 720mV 09347-054 CH1 10A Ω CH3 20V 3 09347-051 4 Figure 55.
PAGE 17
Data Sheet ADP1874/ADP1875 TA = 25°C VREG = 5.5V VREG = 3.6V VREG = 2.7V 570 TRANSCONDUCTANCE (µS) LOW SIDE 4 HIGH SIDE SW NODE 3 2 550 530 510 490 470 450 M M40ns T 29.0% A CH2 4.20V 430 –40 09347-058 CH3 5V MATH 2V 40ns CH2 5V CH4 2V 20 40 60 80 100 680 +125°C +25°C –40°C TRANSCONDUCTANCE (µs) 630 4 120 Figure 61. Transconductance (Gm) vs. Temperature TA = 25°C 16ns (tf,DRVL ) 0 TEMPERATURE (°C) Figure 58.
PAGE 18
ADP1874/ADP1875 Data Sheet ADP1874/ADP1875 BLOCK DIGRAM PGOOD 690mV FB 600mV ADP1874/ADP1875 530mV VREG tON TIMER PRECISION ENABLE VIN C EN TO ENABLE ALL BLOCKS EN_REF I SW INFORMATION LDO VREG R (TRIMMED) tON = 2RC(VOUT/VIN) VREG_IN REF SW FILTER VREG BST BIAS BLOCK AND REFERENCE STATE MACHINE REF_ZERO TON BG_REF ISS SS COMP SS PSM DRVH 300kΩ IN_PSM HS_O IN_SS HS SS_REF IN_HICC COMP LEVEL SHIFT HS SW SW 8kΩ FB PWM IREV TRACK LS LS_O VREG LS DRVL 800kΩ ERROR AMP PGND
PAGE 19
Data Sheet ADP1874/ADP1875 THEORY OF OPERATION PRECISION ENABLE CIRCUITRY The ADP1874/ADP1875 have precision enable circuitry. The precision enable threshold is 630 mV with 30 mV of hysteresis (see Figure 65). Connecting the EN pin to GND disables the ADP1874/ADP1875, reducing the supply current of the device to approximately 140 µA. VREG 10kΩ EN PRECISION ENABLE COMP. STARTUP TO ENABLE ALL BLOCKS 630mV Figure 65.
PAGE 20
ADP1874/ADP1875 Data Sheet ON-BOARD LOW DROPOUT REGULATOR The ADP1874/ADP1875 use an on-board LDO to bias the internal digital and analog circuitry. Connect the VREG and VREG_IN pins together for normal LDO operation for low voltage internal block biasing (see Figure 67). ON-BOARD REGULATOR VIN VREG_IN 09347-168 REF Q1 DRVH Figure 67.
PAGE 21
Data Sheet ADP1874/ADP1875 VALLEY CURRENT LIMIT (A) where: KI is the ratio between the inductor ripple current and the desired average load current (see Figure 70). ICLIM is the desired valley current limit. ILOAD is the current load. Establishing KI helps to determine the inductor value (see the Inductor Selection section), but in most cases KI = 0.33.
PAGE 22
ADP1874/ADP1875 Data Sheet REPEATED CURRENT-LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS OF PULSES IS COUNTED TO REINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE VIOLATION TO COOL DOWN STILL EXISTS 09347-071 CLIM ZERO CURRENT Figure 73.
PAGE 23
Data Sheet ADP1874/ADP1875 As soon as the forward current through the lower side MOSFET decreases to a level where 10 mV = IQ2 × RON(Q2) the zero-cross comparator (or IREV comparator) emits a signal to turn off the lower side MOSFET. From this point, the slope of the inductor current ramping down becomes steeper (see Figure 76) as the body diode of the lower side MOSFET begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted.
PAGE 24
ADP1874/ADP1875 Data Sheet PSEUDO-FIXED FREQUENCY The ADP1874/ADP1875 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the oneshot tON timer that produces a high-side PWM pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state.
PAGE 25
Data Sheet ADP1874/ADP1875 OUTPUT OVERVOLTAGE PGOOD DEASSERT 690mV PGOOD REASSERT HYSTERESIS (50mV) 640mV FB 600mV 530mV 0V PGOOD ASSERTION AT POWER-UP PGOOD DEASSERTION AT POWER DOWN SOFT-START VEXT tPGD tPGD 09347-181 tPGD PGOOD tPGD 0V Figure 80. Power Good Timing Diagram, tPGD = 12 µs (Diagram May Look Disproportionate for Illustration Purposes.) SLAVE VREG 10kΩ EN MASTER PGOOD VREG 10kΩ EN 1.8V VOUT1 (MASTER) 1.
PAGE 26
ADP1874/ADP1875 Data Sheet not recommended to force any voltage on the slave TRACK pin lower than 0.6 V. Figure 84 illustrates a circuit with a ratiometric tracking configuration. Setting RTRK1 > RTRK2 ensures that the slave TRACK voltage will rise up more quickly (to the regulation point) than the master voltage. MASTER VOLTAGE SLAVE VOLTAGE TIME (ms) 09347-085 OUTPUT VOLTAGE (V) The slave output tracks the master output dv/dt until the slave output regulation point is reached.
PAGE 27
Data Sheet ADP1874/ADP1875 APPLICATIONS INFORMATION Table 8. Recommended Inductors FEEDBACK RESISTOR DIVIDER INDUCTOR SELECTION L (µH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by OUTPUT RIPPLE VOLTAGE (ΔVRR) The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V.
PAGE 28
ADP1874/ADP1875 Data Sheet Ceramic capacitors are known to have low ESR. However, there is a trade-off in using the popular X5R capacitor technology because up to 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see Figure 86). Although X7R series capacitors can also be used, the available selection is limited to 22 µF maximum.
PAGE 29
Data Sheet ADP1874/ADP1875 EFFICIENCY CONSIDERATION MOSFET Driver Loss One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process: Other dissipative elements are the MOSFET drivers.
PAGE 30
ADP1874/ADP1875 Data Sheet Diode Conduction Loss INPUT CAPACITOR SELECTION The ADP1874/ADP1875 employ anti cross-conduction circuitry that prevents the upper side and lower side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage.
PAGE 31
Data Sheet ADP1874/ADP1875 THERMAL CONSIDERATIONS The ADP1874/ADP1875 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board LDO, and on-board MOSFET drivers. Because applications may require up to 20 A of load current and be subjected to high ambient temperature, the selection of external upper side and lower side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125°C.
PAGE 32
ADP1874/ADP1875 Data Sheet For example, if the external MOSFET characteristics are θJA (16-lead QSOP) = 104°C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V, then the power loss is [ ( )] PDR( LOSS ) = V DR × f SW C upperFET V DR + I BIAS + [VREG × ( f SW C lowerFET VREG + I BIAS )] Inductor Determine inductor ripple current amplitude as follows: ∆I L ≈ Therefore, calculating for the inductor value = (4.62 × (300 × 10 3 × 3.3 × 10 −9 × 4.
PAGE 33
Data Sheet ADP1874/ADP1875 Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate. C OUT = = (L × I 2 CCOMP = LOAD ) ((VOUT − ∆VOVSHT )2 − (VOUT )2 ) = 1 2πRCOMP f ZERO 1 2 × 3.14 × 60.25 × 103 × 6.25 × 103 1× 10 −6 × (15 A) 2 = 423 pF (1.8 − 45 mV) 2 − (1.8) 2 Loss Calculations = 1.4 mF Duty cycle = 1.8/12 V = 0.15 Choose five 270 µF polymer capacitors. RON (N2) = 5.
PAGE 34
ADP1874/ADP1875 Data Sheet EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 1 kΩ, RON = 5.4 mΩ (BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A. The ADP1875 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Marking Code (First Line/Second Line) SAP Model ADP1874ARQZ-0.3-R7/ ADP1875ARQZ-0.3-R7 ADP1874ARQZ-0.6-R7/ ADP1875ARQZ-0.
PAGE 35
Data Sheet ADP1874/ADP1875 Marking Code (First Line/Second Line) SAP Model ADP1874ARQZ-1.0-R7/ ADP1875ARQZ-1.0-R7 ADP1874 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 1874/1.0 ADP1875 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 1875/1.0 VOUT (V) 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 VIN (V) 5.5 5.5 5.5 5.5 13 13 13 13 13 16.
PAGE 36
ADP1874/ADP1875 Data Sheet LAYOUT CONSIDERATIONS Figure 90 shows the schematic of a typical ADP1874/ADP1875 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.
PAGE 37
ADP1874/ADP1875 09347-093 Data Sheet Figure 92. Layer 2 of ADP1874/ADP1875 Evaluation Board TOP RESISTOR FEEDBACK TAP 09347-094 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK. THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING TO THE ANALOG GROUND PLANE Figure 93. Layer 3 of ADP1874/ADP1875 Evaluation Board Rev.
PAGE 38
ADP1874/ADP1875 Data Sheet BOTTOM RESISTOR TAP TO ANALOG GROUND PLANE 09347-095 PGND SENSE TAP FROM NEGATIVE TERMINALS OF THE OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE OF LAYER 3. Figure 94. Layer 4 (Bottom Layer) of ADP1874/ADP1875 Evaluation Board A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 5).
PAGE 39
Data Sheet ADP1874/ADP1875 DIFFERENTIAL SENSING Because the ADP1874/ADP1875 operate in valley current-mode control, a differential voltage reading is taken across the drain and source of the lower side MOSFET. The drain of the lower side MOSFET should be connected as close as possible to the SW pin (Pin 15) of the IC. Likewise, the source should be connected as close as possible to the PGND pin (Pin 13) of the IC.
PAGE 40
ADP1874/ADP1875 Data Sheet TYPICAL APPLICATION CIRCUITS 12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 12V JP3 CVIN 22µF CPAR 56pF R7 10kΩ VREG ADP1874/ ADP1875 1 VIN 2 COMP 3 EN DRVH 14 4 FB PGND 13 5 GND DRVL 12 6 RES PGOOD 11 7 VREG RTOP 2kΩ VOUT RBOT 1kΩ RRES 100kΩ VREG_IN 8 C2 0.1µF BST 16 C3 22µF CBST 100nF Q1 C5 22µF C6 22µF 1.2µH Q3 5kΩ 10kΩ Q4 + C24 N/A VREG C1 1µF C8 N/A C9 N/A VOUT = 1.8V, 12A + C20 270µF RSNB 2Ω CSNB 1.
PAGE 41
Data Sheet ADP1874/ADP1875 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 13V JP3 CVIN 22µF CPAR 56pF VREG VOUT R7 10kΩ ADP1874/ ADP1875 1 VIN 2 COMP 3 EN RTOP 2kΩ RBOT 1kΩ RRES 100kΩ C1 1µF Q1 FB PGND 13 GND DRVL 12 6 RES PGOOD 11 7 VREG C5 22µF C6 22µF 1.2µH Q3 5kΩ Q4 RSNB 2Ω CSNB 1.5nF 10kΩ VREG C7 22µF C8 N/A C9 N/A VOUT = 1.8V, 12A C20 270µF C24 N/A VREG SS 10 TRACK 9 C4 22µF Q2 SW 15 5 VREG_IN C3 22µF DRVH 14 4 8 C2 0.
PAGE 42
ADP1874/ADP1875 Data Sheet OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 1 8 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 0.041 (1.
PAGE 43
Data Sheet ADP1874/ADP1875 NOTES Rev.