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Synchronous Buck Controller with

Constant On Time and Valley Current Mode

Data Sheet

ADP1878/ADP1879

Rev. B Document Feedback

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FEATURES

Power input voltage range: 2.95 V to 20 V

On-board bias regulator

Minimum output voltage: 0.6 V

0.6 V reference voltage with ±1.0% accuracy

Supports all N-channel MOSFET power stages

Available in 300 kHz, 600 kHz, and 1.0 MHz options

No current sense resistor required

Power saving mode (PSM) for light loads (ADP1879 only)

Resistor programmable current limit

Power good with internal pull-up resistor

Externally programmable soft start

Thermal overload protection

Short-circuit protection

Standalone precision enable input

Integrated bootstrap diode for high-side drive

Starts into a precharged output

Available in a 14-lead LFCSP_WD package

APPLICATIONS

Telecommunications and networking systems

Mid-to-high end servers

Set-top boxes

DSP core power supplies

TYPICAL APPLICATIONS CIRCUIT

Figure 1.

GENERAL DESCRIPTION

The ADP1878/ADP1879 are versatile current-mode, synchronous

step-down controllers. They provide superior transient response,

optimal stability, and current-limit protection by using a constant

on time, pseudo fixed frequency with a programmable current-limit,

current control scheme. These devices offer optimum performance

at low duty cycles by using a valley, current-mode control architec-

ture allowing the ADP1878/ADP1879 to drive all N-channel power

stages to regulate output voltages to as low as 0.6 V.

The ADP1879 is the power saving mode (PSM) version of the

device and is capable of pulse skipping to maintain output

regulation while achieving improved system efficiency at light

loads (see the ADP1879 Power Saving Mode (PSM) section for

more information).

Available in three frequency options (300 kHz, 600 kHz, and

1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well

suited for a wide range of applications that require a single input

power supply range from 2.95 V to 20 V. Low voltage biasing is

supplied via a 5 V internal low dropout regulator (LDO). In

addition, soft start programmability is included to limit input

inrush current from the input supply during startup and to

provide reverse current protection during precharged output

conditions. The low-side current sense, current gain scheme and

integration of a boost diode, together with the PSM/forced

pulse-width modulation (PWM) option, reduce the external

device count and improve efficiency.

The ADP1878/ADP1879 operate over the −40°C to +125°C

junction temperature range and are available in a 14-lead

LFCSP_WD package.

Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (V

OUT

= 1.8 V, 300 kHz)

COMP

BST

DRVH

GND

VREG

RES

DRVL

PGND

VIN

VREG

VREG2

BOT

TOP

OUT

10k

REG

OUT

BST

LOAD

= 2.95V TO 20

ADP1878/

ADP1879

RES

PGOOD

PGD

EXT

09441-001

100

10 100 1k 10k 100k

EFFICIENCY (%)

LOAD CURRENT (mA)

= 25°C

OUT

= 1.8V

= 300kHz

WÜRTH INDUCTOR:

744325120, L = 1.2µH, DCR = 1.8m

INFINEON FETs:

BSC042N03MS G (UPPER/LOWER)

= 5V (PSM)

= 13V (PSM)

= 16.5V (PSM)

= 13V

= 16.5V

09441-102

Summary of content (40 pages)

PAGE 1
FEATURES TYPICAL APPLICATIONS CIRCUIT Power input voltage range: 2.95 V to 20 V On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.
PAGE 2
ADP1878/ADP1879 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pseudo Fixed Frequency............................................................ 22 Applications ....................................................................................... 1 Power-Good Monitoring ........................................................... 23 Typical Applications Circuit.....................................................
PAGE 3
Data Sheet ADP1878/ADP1879 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V, BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Table 1.
PAGE 4
ADP1878/ADP1879 Data Sheet Parameter ADP1878ACPZ-0.6-R7/ ADP1879ACPZ-0.6-R7 On Time Minimum On Time Minimum Off Time ADP1878ACPZ-1.0-R7/ ADP1879ACPZ-1.
PAGE 5
Data Sheet ADP1878/ADP1879 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VREG to PGND, GND VIN, EN, PGOOD to PGND FB, COMP, RES, SS to GND DRVL to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND PGOOD Input Current θJA (14-Lead LFCSP_WD) 4-Layer Board Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating −0.3 V to +6 V −0.3 V to +28 V −0.3 V to (VREG + 0.3 V) −0.3 V to (VREG + 0.3 V) −2.
PAGE 6
ADP1878/ADP1879 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP1878/ADP1879 VIN 1 14 BST COMP 2 13 SW EN 3 12 DRVH FB 11 PGND 4 GND 5 10 RES 6 9 DRVL PGOOD VREG 7 8 SS NOTES 1. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PIN (GND). 09441-003 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 7
Data Sheet ADP1878/ADP1879 VIN = 16.5V VIN = 13V TA = 25°C VOUT = 0.8V fSW = 300kHz WÜRTH INDUCTOR: 744325072, L = 0.72µH, DCR = 1.3mΩ INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 100k EFFICIENCY (%) 09441-005 EFFICIENCY (%) LOAD CURRENT (mA) EFFICIENCY (%) VIN = 16.5V TA = 25°C VOUT = 7V fSW = 300kHz WÜRTH INDUCTOR: 7443551200, L = 2.0µH, DCR = 2.
PAGE 8
100 95 90 85 80 75 70 65 VIN = 13V (PSM) 60 55 50 45 40 35 30 VIN = 16.5V (PSM) 25 20 15 10 5 0 10 100 Data Sheet 0.807 0.806 VIN = 13V 0.805 VIN = 16.5V TA = 25°C VOUT = 0.8V fSW = 1.0MHz 10k 100k LOAD CURRENT (mA) 0.798 0.797 0.796 0.792 VIN = 13V +125°C +25°C –40°C 0 2000 VIN = 16.5V +125°C +25°C –40°C 4000 6000 8000 10,000 LOAD CURRENT (mA) 1.821 VIN = 13V VIN = 16.5V TA = 25°C VOUT = 1.8V fSW = 1.0MHz WÜRTH INDUCTOR: 744303022, L = 0.22µH, DCR = 0.
PAGE 9
Data Sheet ADP1878/ADP1879 0.808 0.807 0.805 0.806 0.803 OUTPUT VOLTAGE (V) FREQUENCY (kHz) 0.804 0.802 0.800 0.798 0.801 0.799 0.797 0.795 0.793 0.796 0.791 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 0.787 0 4000 6000 8000 10,000 Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V 1.820 1.818 1.816 1.814 1.812 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 1.788 1.786 1.784 1.782 1.780 1.778 1.776 1.774 1.772 1.
PAGE 10
ADP1878/ADP1879 Data Sheet 900 601.0 599.5 VREG = 5V, VIN = 13V 599.0 598.5 598.0 840 820 800 780 760 740 597.5 25.0 57.5 90.0 700 13.0 09441-022 –7.5 122.5 TEMPERATURE (°C) +125°C +25°C –40°C 14.5 15.0 15.5 16.0 16.5 Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz, VIN Range = 13 V to 16.5 V 280 NO LOAD VIN = 13V VIN = 20V VIN = 16.5V 265 +125°C +25°C –40°C 305 FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) 315 14.0 VIN (V) Figure 22. Feedback Voltage vs.
PAGE 11
Data Sheet VIN = 13V VIN = 16.5V 334 +125°C +25°C –40°C 326 FREQUENCY (kHz) FREQUENCY (kHz) 330 322 318 314 310 306 302 0 09441-028 298 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) +125°C +25°C –40°C 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V 850 +125°C +25°C –40°C VIN = 13V VIN = 16.5V VIN = 13V VIN = 16.5V 0 Figure 28. Frequency vs.
PAGE 12
ADP1878/ADP1879 Data Sheet 1450 82 VIN = 13V VIN = 16.5V 1400 +125°C +25°C –40°C MAXIMUM DUTY CYCLE (%) 1300 1250 1200 1150 1100 76 74 72 70 68 66 1050 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) 62 5.5 09441-034 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 VIN (V) Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN) Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V 2.658 680 2.657 630 VREG = 2.7V VREG = 3.6V VREG = 5.
PAGE 13
Data Sheet 80 +125°C +25°C –40°C RECTIFIER DROP (mV) 640 560 480 400 320 240 160 400 500 600 700 800 900 1000 FREQUENCY (kHz) 1200 1120 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz 48 40 32 24 16 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VREG (V) Figure 43. Low-Side MOSFET Body Diode Conduction Time vs. VREG TA = 25°C OUTPUT VOLTAGE 1 1040 RECTIFIER DROP (mV) 56 8 2.7 Figure 40. Internal Rectifier Drop vs.
PAGE 14
ADP1878/ADP1879 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE INDUCTOR CURRENT 12A NEGATIVE STEP 1 SW NODE 1 3 SW NODE LOW SIDE 3 M400ns CH4 100mV A CH3 2.20V B W T 30.6% CH1 10A Ω CH3 20V Figure 46. CCM Operation at Heavy Load, 12 A (See Figure 95 for Application Circuit) CH2 200mV CH4 5V B W M20µs A CH1 3.40A T 48.2% 09441-049 CH1 5A Ω CH3 10V 09441-046 4 Figure 49.
PAGE 15
Data Sheet ADP1878/ADP1879 OUTPUT VOLTAGE OUTPUT VOLTAGE 2 1 INDUCTOR CURRENT 12A NEGATIVE STEP 2 1 SW NODE LOW SIDE 4 3 SW NODE LOW SIDE CH2 200mV CH4 5V B W M10µs A CH1 5.60A T 23.8% CH1 2V BW CH2 5A Ω CH3 10V CH4 5V Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, 12 A (See Figure 95 Application Circuit) M2ms T 32.8% A CH1 720mV 09441-055 CH1 10A Ω CH3 20V 3 09441-052 4 Figure 55.
PAGE 16
ADP1878/ADP1879 Data Sheet TA = 25°C VREG = 5.5V VREG = 3.6V VREG = 2.7V 570 TRANSCONDUCTANCE (µS) LOW SIDE 4 HIGH SIDE SW NODE 3 2 550 530 510 490 470 450 M M40ns T 29.0% A CH2 4.20V 430 –40 09441-058 CH3 5V MATH 2V 40ns CH2 5V CH4 2V 20 40 60 80 100 680 +125°C +25°C –40°C TRANSCONDUCTANCE (µS) 630 22ns (tpdhDRVH ) HIGH SIDE 25ns (tr,DRVH ) SW NODE 3 2 530 480 430 380 HS MINUS SW CH2 5V CH3 5V CH4 2V MATH 2V 40ns M40ns T 29.0% A CH2 4.20V 330 2.7 09441-059 M 580 3.
PAGE 17
Data Sheet ADP1878/ADP1879 THEORY OF OPERATION BLOCK DIAGRAM PGOOD 690mV FB 600mV ADP1878/ADP1879 530mV VREG tON TIMER PRECISION ENABLE EN C TO ENABLE ALL BLOCKS THRESHOLD/ HYSTERESIS 630mV VIN I SW INFORMATION LDO VREG R (TRIMMED) tON = 2RC(VOUT/VIN) REF SW FILTER VREG BST BIAS BLOCK AND REFERENCE STATE MACHINE REF_ZERO TON BG_REF ISS SS COMP SS PSM IN_PSM IN_SS DRVH 300kΩ HS_0 HS LEVEL SHIFT SS_REF COMP COMP PWM FB SW IREV SW 8kΩ LS LS_0 VREG LS ERROR AMP 0.
PAGE 18
ADP1878/ADP1879 Data Sheet STARTUP PRECISION ENABLE CIRCUITRY Each ADP1878/ADP1879 has an internal regulator (VREG) for biasing and supplying power for the integrated N-channel MOSFET drivers. Place a bypass capacitor directly across the VREG (Pin 7) and PGND (Pin 13) pins. Included in the powerup sequence is the biasing of the current sense amplifier, the current sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier.
PAGE 19
Data Sheet ADP1878/ADP1879 Table 5. Power Input and LDO Output Configurations VREG Float Connect to VIN <5.5 V VIN ranging above and below 5.5 V Float Float PGND ADC CS GAIN SET 0.4V RES Figure 69. RES Detect Circuit for Current Sense Gain Programming THERMAL SHUTDOWN Thermal shutdown is a protection feature that prevents the IC from damage caused by a very high operating junction temperature. If the junction temperature of the device exceeds 155°C, the device enters the thermal shutdown state.
PAGE 20
ADP1878/ADP1879 Data Sheet 1.4 V where: RON is the channel impedance of the low-side MOSFET. ACS is the current sense gain multiplier (see Table 6 and Table 7). Although the ADP1878/ADP1879 have only four discrete current sense gain settings for a given RON variable, Table 7 and Figure 71 outline several available options for the valley current setpoint based on various RON values. The valley current limit is programmed as listed in Table 7 and shown in Figure 71.
PAGE 21
Data Sheet ADP1878/ADP1879 REPEATED CURRENT-LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS OF PULSES IS COUNTED TO REINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE TO COOL DOWN VIOLATION STILL EXISTS 09441-073 CLIM ZERO CURRENT Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation HS A current-limit violation occurs when the current across the source and drain of the low-side MOSFET exceeds the currentlimit setpoint.
PAGE 22
ADP1878/ADP1879 Data Sheet ANOTHER tON EDGE IS TRIGGERED WHEN VOUT FALLS BELOW REGULATION SW The tON timer uses a feedforward technique that, when applied to the constant on-time control loop, makes it a pseudo fixed frequency to a first-order approximation. tON Second-order effects, such as dc losses in the external power MOSFETs (see the Efficiency Consideration section), cause some variation in frequency vs. load current and line voltage. These effects are shown in Figure 23 to Figure 34.
PAGE 23
Data Sheet ADP1878/ADP1879 is sensed through the counter action upswing of the output (COMP) of the error amplifier. The result is a convergence of these two signals (see Figure 78), which allows an instantaneous increase in switching frequency during the positive load transient event. In summary, a positive load step causes VOUT to transient down, which causes COMP to transient up and, therefore, shortens the off time.
PAGE 24
ADP1878/ADP1879 Data Sheet APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER Table 8. Recommended Inductors The required resistor divider network can be determined for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V. Selecting values for RT and RB determine the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined through the following expression: L (µH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.
PAGE 25
Data Sheet ADP1878/ADP1879 Ceramic capacitors are known to have low ESR. However, there is a trade-off in using the popular X5R capacitor technology because as much as 80% of its capacitance may be lost due to derating as the voltage applied across the capacitor is increased (see Figure 82). Although X7R series capacitors can also be used, the available selection is limited to 22 µF maximum.
PAGE 26
ADP1878/ADP1879 Data Sheet 800 An important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents of up to 20 A, the following are important MOSFET parameters that aid in the selection process: 720     VGS (TH) is the MOSFET voltage applied between the gate and the source that starts channel conduction.
PAGE 27
Data Sheet ADP1878/ADP1879 The amount of loss through the body diode of the low-side MOSFET during the anti overlap state is given by the following expression: 2 where: tBODY(LOSS) is the body conduction time (refer to Figure 84 for dead time periods). tSW is the period per switching cycle. VF is the forward drop of the body diode during conduction. (Refer to the selected external MOSFET data sheet for more information about the VF parameter.
PAGE 28
ADP1878/ADP1879 Data Sheet power dissipation across the internal LDO. Equation 3 shows the power dissipation calculations for the integrated drivers and for the internal LDO. Table 9 lists the thermal impedance for the ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD. The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship: Table 9.
PAGE 29
Data Sheet ADP1878/ADP1879 The rise in package temperature (for a 14-lead LFCSP_WD) is Current-Limit Programming The valley current is approximately TR = θJA × PDR(LOSS) 15 A − (5 A × 0.5) = 12.5 A = 30°C × 132.05 mW = 4.0°C Assuming a maximum ambient temperature environment of 85°C, TJ = TR × TA = 4.0°C + 85°C = 89.0°C, which is below the maximum junction temperature of 125°C. DESIGN EXAMPLE The ADP1878/ADP1879 are easy to use, requiring only a few design criteria.
PAGE 30
ADP1878/ADP1879 Data Sheet Feedback Resistor Network Setup Loss Calculations Choosing RB = 1 kΩ as an example. Calculate RT as follows: Duty cycle = 1.8/12 V = 0.15 𝑅𝑇 = 1 kΩ × (1.8 V − 0.6 V) = 2 kΩ 0.6 V RON(N2) = 5.4 mΩ tBODY(LOSS) = 20 ns (body conduction time) Compensation Network To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current sense gain variable are required.
PAGE 31
Data Sheet ADP1878/ADP1879 EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 1kΩ, RON = 5.4 mΩ (BSC042N03MS G), VREG = 5 V (float), and a maximum load current of 14 A. The ADP1879 models listed in Table 10 are the PSM versions of the device. Table 10. External Component Values Model ADP1878ACPZ-0.3-R7/ ADP1879ACPZ-0.3-R7 ADP1878ACPZ-0.6-R7/ ADP1879ACPZ-0.6-R7 ADP1878ACPZ-1.0-R7/ ADP1879ACPZ-1.0-R7 VOUT (V) 0.
PAGE 32
ADP1878/ADP1879 Data Sheet Table 11. Recommended Inductors L (μH) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (mΩ) 0.33 0.33 0.8 1.65 1.6 1.8 3.8 3.2 2.6 ISAT (A) 55 30 50 35 32 25 16 24 23 27.5 Dimension (mm) 10.2 × 7 10.2 × 7 14.2 × 12.8 10.5 × 10.2 14 × 12.8 10.5 × 10.2 10.2 × 10.2 14 × 12.8 10.2 × 10.
PAGE 33
Data Sheet ADP1878/ADP1879 LAYOUT CONSIDERATIONS Figure 86 shows the schematic of a typical ADP1878/ADP1879 used for a high current application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor.
PAGE 34
Data Sheet 09441-088 ADP1878/ADP1879 Figure 88. Layer 2 of Evaluation Board TOP RESISTOR FEEDBACK TAP 09441-089 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK. THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING TO THE ANALOG GROUND PLANE Figure 89. Layer 3 of Evaluation Board Rev.
PAGE 35
Data Sheet ADP1878/ADP1879 BOTTOM RESISTOR TAP TO ANALOG GROUND PLANE 09441-090 PGND SENSE TAP FROM NEGATIVE TERMINALS OF THE OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE OF LAYER 3. Figure 90. Layer 4 (Bottom Layer) of Evaluation Board IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND).
PAGE 36
ADP1878/ADP1879 Data Sheet SW Figure 91. Primary Current Pathways During the On State of the High-Side MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1878/ADP1879 operate in valley current-mode control, a differential voltage reading is taken across the drain and source of the low-side MOSFET. Connect the drain of the low-side MOSFET s as close as possible to the SW pin (Pin 13) of the IC.
PAGE 37
Data Sheet ADP1878/ADP1879 TYPICAL APPLICATION CIRCUITS 12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 12V JP3 CVIN 22µF CPAR 56pF R7 10kΩ VREG ADP1878/ ADP1879 1 RBOT 1kΩ RRES 100kΩ C2 0.1µF BST 14 2 COMP 3 EN DRVH 12 4 FB PGND 11 5 GND DRVL 10 RTOP 2kΩ VOUT VIN 6 RES 7 VREG CBST 100nF Q1 C4 22µF C6 22µF 1.
PAGE 38
ADP1878/ADP1879 Data Sheet 300 kHz HIGH CURRENT APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 13V JP3 CVIN 22µF CPAR 56pF VREG VOUT R7 10kΩ ADP1878/ ADP1879 1 2 COMP 3 EN RTOP 2kΩ RBOT 1kΩ RRES 100kΩ C2 0.1µF C1 1µF VIN BST 14 FB PGND 11 GND DRVL 10 7 VREG PGOOD 9 SS 8 C5 22µF C6 22µF 1.2µH Q3 5kΩ C7 22µF C8 N/A C9 N/A Q2 SW 13 5 RES Q1 DRVH 12 4 6 CBST 100nF C4 22µF Q4 RSNB 2Ω CSNB 1.5nF VOUT = 1.
PAGE 39
Data Sheet ADP1878/ADP1879 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 4.10 4.00 3.90 3.40 3.30 3.15 0.10 REF 0.20 MIN 8 0.30 REF TOP VIEW 0.80 0.75 0.70 SEATING PLANE END VIEW 7 0.50 0.40 0.30 SIDE VIEW 0.30 0.25 0.20 0.50 BSC 1.80 1.70 1.55 EXPOSED PAD 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.15 REF 1 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 40
ADP1878/ADP1879 Data Sheet ORDERING GUIDE Model 1 ADP1878ACPZ-0.3-R7 ADP1878ACPZ-0.6-R7 ADP1878ACPZ-1.0-R7 ADP1878-0.3-EVALZ ADP1878-0.6-EVALZ ADP1878-1.0-EVALZ ADP1879ACPZ-0.3-R7 ADP1879ACPZ-0.6-R7 ADP1879ACPZ-1.0-R7 ADP1879-0.3-EVALZ ADP1879-0.6-EVALZ ADP1879-1.