Datasheet

EVAL-ADP2118
Rev. 0 | Page 9 of 16
LAYOUT GUIDELINES
The input decoupling capacitor (C
IN
) should be as close as
possible to the PVIN and PGND pins. Make the loop composed
of PVIN, PGND, and C
IN
as small as possible.
The VIN filter needs to be placed as close as possible to the
VIN pin.
A ground plane is recommended to minimize noise and
maximize heat dissipation. If a ground plane layer is not used,
the analog ground (GND) and the power ground (PGND)
should be separated and tied together at the output capacitor
terminal.
Flood all unused areas on all layers with copper to reduce
the temperature rise of power components. The copper areas
must be connected to a dc net, for example, PVIN, V
OUT
,
PGND, or GND.
Connect the FB pin directly to the feedback resistor divider or
to the output if the fixed output version is used. The feedback
node must be kept well away from noise sources like the
switching node.
An RC snubber between SW and PGND can reduce spikes at
the switching node under heavy load conditions.