Datasheet

ADP2302/ADP2303 Data Sheet
Rev. A | Page 20 of 28
DESIGN EXAMPLE
This section provides the procedures to select the external compo-
nents, based on the example specifications listed in Table 10.
The schematic for this design example is shown in Figure 51.
Because the output current is 3 A, the ADP2303 is chosen for
this application.
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter Specification
Additional
Requirements
Input Voltage, V
IN
12.0 V ± 10% None
Output Voltage, V
OUT
3.3 V, 3 A, 1% V
OUT
ripple
at full load condition
None
Programmable
UVLO Voltage
V
IN
start-up voltage
approximately 7.8 V
None
PGOOD Not used None
CATCH DIODE SELECTION
Select the catch diode. A Schottky diode is recommended for best
efficiency because it has a low forward voltage drop and faster
switching speed. The average current of the catch diode in
normal operation, with a typical Schottky diode forward
voltage, can be calculated using the following equation:
(max))(
1
LOAD
DIN
D
OUT
AVGDIODE
I
VV
VV
I 











where:
V
OUT
= 3.3 V.
V
IN
= 12 V.
I
LOAD(max)
= 3 A.
V
D
= 0.4 V.
Therefore, I
DIODE(AVG)
= 2.1 A.
In this case, selecting a SSB43L, 4.0 A, 30 V surface-mount
Schottky diode results in more reliable operation.
INDUCTOR SELECTION
Select the inductor by using the following equation:















DIN
D
OUT
sw
LOAD
OUT
IN
VV
VV
fI
VV
L
(max)
3.0
where:
V
OUT
= 3.3 V.
V
IN
= 12 V.
I
LOAD(max)
= 3 A.
V
D
= 0.4 V.
f
SW
= 700 kHz.
This results in L = 4.12 µH. The closest standard value is 4.7 µH;
therefore, I
RIPPLE
= 0.7 A.
The inductor peak current is calculated using the following
equation:
2
(max)
RIPPLE
LOAD
PEAK
I
II


where:
I
LOAD(max)
= 3 A.
I
RIPPLE
= 0.7 A.
The calculated peak current for the inductor is 3.4 A. Therefore,
in this application, select VLF10040T-4R7N5R4 as the inductor.
OUTPUT CAPACITOR SELECTION
Select the output capacitor based on the minimum output
voltage ripple requirement, according to the following equation:











OUT
C
OUT
sw
RIPPLERIPPLE
ESR
Cf
IV
8
1
where:
ΔI
RIPPLE
= 0.7 A.
f
SW
= 700 kHz.
V
RIPPLE
= 33 mV (1% of output voltage).
If ESR of the ceramic capacitor is 3 m, then C
OUT
= 4 µF.
Because the output capacitor is one of two external components
that control the loop stability and according to the recommended
external components in Table 11, choose two 47 µF capacitor
with a 6.3 V voltage rating in this application.
RESISTIVE VOLTAGE DIVIDER SELECTION
The output feedback resistive voltage divider is









BOT
TOP
OUT
R
R
V 1V800.0
For the 3.3 V output voltage, choose R
TOP
= 31.6 k and
R
BOT
= 10.2 k as the feedback resistive voltage divider
according to the recommended values in Table 11.
The resistive voltage divider for the programmable V
IN
start-up
voltage is
V2.1A2.1
V2.1










EN1
EN2
STARTUP
R
R
V
If V
STARTUP
= 7.8 V, choose R
EN2
= 10.2 k, and then calculate
R
EN1
, which, in this case, is 56 k.