Datasheet

Data Sheet ADP2323
Rev. A | Page 19 of 32
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
The ADP2323 is supported by the ADIsimPower design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic and bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count
while taking into consideration the operating conditions
and limitations of the IC and all real external components. For
more information about ADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board
through the tool.
INPUT CAPACITOR SELECTION
The input decoupling capacitor attenuates high frequency noise
on the input and acts as an energy reservoir. This capacitor
should be a ceramic capacitor in the range of 10 µF to 47 µF and
must be placed close to the PVINx pin. The loop composed of
this input capacitor, high-side NFET, and low-side NFET must
be kept as small as possible. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The
rms current rating of the input capacitor should be larger than
the following equation:
( )
DDII
OUT
rmsC
IN
−××= 1
_
OUTPUT VOLTAGE SETTING
The output voltage of the ADP2323 can be set by an external
resistive divider using the following equation:








+×=
BOT
TOP
OUT
R
R
V 16.0
To limit output voltage accuracy degradation due to FBx pin
bias current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that R
BOT
is less than 30 kΩ.
Table 8 provides the recommended resistive divider for various
output voltage options.
Table 8. Resistive Divider for Various Output Voltages
V
OUT
(V)
R
TOP
, ±1% (kΩ)
R
BOT
, ±1% (kΩ)
1.0 10 15
1.2 10 10
1.5 15 10
1.8 20 10
2.5 47.5 15
3.3 10 2.21
5.0 22 3
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2323 is typically 130 ns. The
minimum output voltage in CCM mode at a given input voltage
and frequency can be calculated by using the following equation:
V
OUT_MIN
= V
IN
× t
MIN_ON
× f
SW
− (R
DSON1
− R
DSON2
) × I
OUT_MIN
×
t
MIN_ON
× f
SW
− (R
DSON2
+ R
L
) × I
OUT_MIN
where:
V
OUT_MIN
is the minimum output voltage.
t
MIN_ON
is the minimum on time.
I
OUT_MIN
is the minimum output current.
f
SW
is the switching frequency.
R
DSON1
is the high-side MOSFET on resistance.
R
DSON2
is the low-side MOSFET on resistance.
R
L
is the series resistance of output inductor.
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
150 ns and the maximum duty is typically 90% in the ADP2323.
The maximum output voltage that is limited by the minimum off
time at a given input voltage and frequency can be calculated
using the following equation:
V
OUT_MAX
= V
IN
× (1 – t
MIN_OFF
× f
SW
) – (R
DSON1
– R
DSON2
) ×
I
OUT_MAX
× (1 – t
MIN_OFF
× f
SW
) – (R
DSON2
+ R
L
) × I
OUT_MAX
where:
V
OUT_MAX
is the maximum output voltage.
t
MIN_OFF
is the minimum off time.
I
OUT_MAX
is the maximum output current.
The maximum output voltage limited by the maximum duty
cycle at a given input voltage can be calculated by using the
following equation:
V
OUT_MAX
= D
MAX
× V
IN
where D
MAX
is the maximum duty.
As the previous equations show, reducing the switching frequency
alleviates the minimum on time and minimum off time
limitation.
CURRENT-LIMIT SETTING
The ADP2323 has three selectable current-limit thresholds.
Make sure that the selected current-limit value is larger than the
peak current of the inductor, I
PEAK
.