Datasheet
ADP2370/ADP2371 Data Sheet
Rev. C | Page 20 of 32
THEORY OF OPERATION
SLOPE COM
P
OSCILLA
T
OR
DE
FAUL
T = 1.2MHz
VOUT ÷ 2 FREQUENCY
FOLDBACK
CONTRO
L
LOGIC
ADP2371
ON
LY
SOFT
START
1.2V
EN
VIN
SW
PGND
FB
SYNC
FSEL
PG
1.0V
S
TANDB
Y
EN_PREC
VIN
200mA
Kr
UVLO
VIN
PWM
PSM
0.808V
0.8V
VIN
1.2A
VIN
5V
REG
VIN
2.95V
0.736V
0.8V
0.696V
150°C
135°C
H = FPWM
L
= PWM/PSM
H = 1.2MHz
L
= 600kHz
THSD
FB
I
SLOPE
RDS
ON
× Kr
RDS
ON
× Kr
P_I
LIMIT
N_I
LIMIT
–0.5
A
– (PWM)
0
A – (PSM)
I
MIN
V
SW
g
M
V
COM
P
I
COM
P
V
TO
L
09531-071
Figure 71. Functional Block Diagram
The ADP2370/ADP2371 use a high speed, current mode, con-
stant frequency PWM control scheme for excellent stability and
transient response. To ensure the longest battery life in portable
applications, the ADP2370/ADP2371 has a power saving mode.
Under light load conditions, the output capacitor is charged as
needed to maintain regulation; otherwise, the ADP2370/ADP2371
enter sleep mode, a low 14 μA quiescent state. The architecture
ensures smooth transitions from PWM mode to and from PSM,
and maintains high efficiencies at light loads. The following sec-
tions describe the two modes of operation and provide detailed
descriptions of the ADP2370/ADP2371 features.
PWM OPERATION
The ADP2370/ADP2371 PWM mode is a fixed frequency,
1.2 MHz typical, current mode architecture. Use the SYNC pin
to synchronize the regulator to an external clock frequency or
use the FSEL pin to select an internal clock frequency of
600 kHz or 1.2 MHz.
The ADP2370/ADP2371 use a constant slope compensation
scheme where the inductor scales with the output voltage. The
equation for choosing the inductor for a particular output
voltage is
SW
OUT
f
V
L
×
×
=
478.0
2.1
See the Applications Information section for details regarding
choosing an appropriate inductor value.
Cycle to cycle operation of the PWM mode begins with the
falling edge of the internal clock. Note that when using an
external clock, the rising edge synchronizes the regulator and
the falling edge is determined by the internal clock, typically a
25 ns pulse width. The falling edge of the clock starts the cycle
by turning on the high-side switch, which produces a positive
di/dt current in the inductor. The PWM comparator controls
when the high-side switch turns off. The positive input of the
comparator monitors the peak inductor current via the SW node.