Datasheet

Data Sheet ADP2370/ADP2371
Rev. C | Page 21 of 32
The negative side of the comparator input voltage is set by the
voltage control loop minus the slope compensation. When the
high-side switch turns off, the low-side switch turns on for the
remainder of the clock period.
While in PWM/PSM mode, the low-side switch turns off when
the inductor current reaches zero, operating in discontinuous
conduction (DCC) mode. If SYNC is tied high to force the device
into PWM only mode, the low-side switch stays on until the
next clock cycle or until the inductor current reaches the
negative current limit.
PSM OPERATION
The ADP2370/ADP2371 smoothly transition to the variable
frequency PSM operation. The ADP2370/ADP2371 select a
minimum current value, I
MIN
, for the peak current of the inductor
based on the input and output voltages. The design of the I
MIN
value is based on the recommended inductor values. Deviating
from the recommended inductor value for a particular output
voltage results in shifting the PSM to PWM threshold and could
result in the device entering DCC mode.
As long as the required peak inductor current is above I
MIN
, the
regulator remains in PWM mode. As the load decreases, the
PSM circuitry prevents the peak inductor current from dropping
below the PSM peak current value. This circuitry causes the
regulator to supply more current to the output filter than the
load requires, resulting in the output voltage increasing and the
output of the internal compensation node of the error amplifier,
V
COMP
, decreasing.
When the FB pin voltage rises above 1% of the nominal output
voltage and the V
COMP
node voltage is below a predetermined
PSM threshold voltage level, the regulator enters sleep mode.
While in sleep mode, the high-side and low-side switches and a
majority of the circuitry are disabled to allow for a low sleep
mode quiescent current as well as high efficiency performance.
During sleep mode, the output voltage decreases as the output
capacitor discharges into the load. Fixed frequency operation
starts when the FB voltage reaches the nominal output voltage.
When the load requirement increases past the I
MIN
peak current
level, the V
COMP
node rises and the PWM control loop sets the
duty cycle. While the part is entering and exiting sleep mode,
the PSM voltage ripple is larger than 1% because of the delay in
the comparators.
Figure 72 and Figure 73 illustrate how the output voltage and
inductor current change with loads and transitions in and out of
PSM operation. The output voltage ripple in PSM is ~40 mV p-p,
and the ripple in PWM is <10 mV p-p.
M20.00µs A CH1
156mA
T 50.40%
09531-072
CH1 200mA Ω
B
W
CH3 200mA Ω
B
W
CH2 50.0mV
B
W
LOAD CURRENT
V
OUT
INDUCTOR CURRENT
1
2
3
Figure 72. PSM to PWM Transition Waveforms, V
OUT
= 1.8 V,
10 mA Load to 300 mA Load
M20.00µs A CH1
156mA
T 50.40%
09531-073
CH1 200mA Ω
B
W
CH3 200mA Ω
B
W
CH2 50.0mV
B
W
V
OUT
INDUCTOR CURRENT
1
2
3
LOAD CURRENT
Figure 73. PWM to PSM Transition Waveforms, V
OUT
= 1.8 V,
300 mA Load to 10 mA Load