Datasheet

ADP2370/ADP2371 Data Sheet
Rev. C | Page 30 of 32
0
0.2
0.60.4 0.8 1.0
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
09531-089
6400mm
2
500
mm
2
100
mm
2
T
J
M
A
X
85
95
105
1
15
125
135
Figure 89. Junction Temperature vs. Power Dissipation, T
A
= 85°C
In cases where the board temperature is known, use the thermal
characterization parameter, Ψ
JB
, to estimate the junction temper-
ature rise. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
)
using the formula:
T
J
= T
B
+ (P
D
× Ψ
JB
) (5)
The typical Ψ
JB
value for the 8-lead, 3 mm × 3 mm LFCSP is
22.2° C / W.
09531-090
20
40
60
80
100
120
140
0 0.5 1.0 1.5 2.0
2.5
3.0 3.5 4.0 4.5 5.0
JUNCTION TEMPERATURE (°C)
T
OTAL POWER DISSI
PATION (W)
25
°C
50°C
65
°C
85
°C
T
J
MAX
Figure 90. Junction Temperature vs. Power Dissipation,
Different Board Temperatures
PCB LAYOUT CONSIDERATIONS
Improve heat dissipation from the package by increasing
the amount of copper attached to the pins of the ADP2370/
ADP2371. However, as listed in Table 8, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Poor layout can affect the ADP2370/ADP2371 buck performance
causing electromagnetic interference (EMI), poor electromagnetic
compatibility (EMC) performance, ground bounce, and voltage
losses; thus, regulation and stability can be affected. Implement
a good PCB layout to ensure optimum performance by applying
the following rules:
• Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and long, large tracks act like
antennas.
• Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
• Use a ground plane with several vias connected to the
component-side ground to reduce noise interference on
sensitive circuit nodes.
• Use of 0402-size or 0603-size capacitors achieves the smallest
possible footprint solution on boards where area is limited.