Datasheet

ADP2370/ADP2371 Data Sheet
Rev. C | Page 4 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OSCILLATOR
Oscillator Frequency f
OSC
FSEL = V
IN
, 3.2 V ≤ V
IN
≤ 15 V 1.0 1.2 1.4 MHz
FSEL = 0 V, 3.2 V ≤ V
IN
≤ 15 V 500 600 700 kHz
Frequency Synchronization Range f
SYNC_RANGE
FSEL = 0 V, 3.2 V ≤ V
IN
≤ 15 V 400 800 kHz
FSEL = V
IN
, 3.2 V ≤ V
IN
≤ 15 V
0.8
1.6
MHz
Synchronization Threshold
High SYNC
HIGH
3.2 V ≤ V
IN
≤ 15 V 1.2 V
Low SYNC
LOW
3.2 V ≤ V
IN
≤ 15 V 0.4 V
Hysteresis SYNC
HYS
3.2 V ≤ V
IN
≤ 15 V 200 mV
Typical Sync Duty Cycle Range SYNC
DUTY
V
IN
(1.2 MHz), 3.2 V ≤ V
IN
≤ 5 V, FSEL = V
IN
20 55 %
V
IN
(1.2 MHz), 5 V ≤ V
IN
≤ 15 V, FSEL = V
IN
20 70 %
SYNC Pin Leakage Current SYNC
LKG
SYNC = 0 V or SYNC = V
IN
0.05 1 μA
FSEL Threshold 3.2 V ≤ V
IN
≤ 15 V
High FESL
HIGH
1 V
Low FSEL
LOW
0.4 V
Hysteresis FSEL
HYS
125 mV
FSEL Pin Leakage Current FSEL
LKG
FSEL = 0 V or FSEL = V
IN
0.04 1 μA
POWER GOOD (PG PIN)
PG Threshold
3.2 V ≤ V
IN
≤ 15 V
Rising PG
RISE
92 95 %
Falling PG
FAL L
82.5 87 %
Hysteresis PG
HYS
5 %
PG Output Low PG
LOW
Pull-up current < 1 mA 0.3 V
PG Delay
Rising PG
DELAYRISE
V
OUT
crossing PG rising threshold, pull-up
current < 1 mA
20 μs
Falling PG
DELAYFALL
V
OUT
crossing PG falling threshold, pull-up
current < 1 mA
0.5 μs
PG Leakage PG
LKG
0.04 1 μA
UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage Rising UVLO
RISE
3.19 V
Input Voltage Falling UVLO
FAL L
2.80 V
Hysteresis
UVLO
HYS
190
mV
ENABLE INPUT STANDBY (EN PIN) 3.2 V ≤ V
IN
≤ 15 V
EN Input Logic
V
High EN
STBY-HIGH
1
Low EN
STBY-LOW
0.4 V
Hysteresis EN
STBY-HYS
125 mV
ENABLE INPUT PRECISION (EN PIN) 3.2 V ≤ V
IN
≤ 15 V
EN Input Logic
High EN
HIGH
1.135 1.2 1.26 V
Low EN
LOW
1.045 1.1 1.155 V
Hysteresis EN
HYS
100 mV
EN Input Leakage Current I
EN-LKG
EN = V
IN
or GND 0.05 1 µA
EN Input Delay Time TI
EN-DLY
For V
OUT
= 0 V to 0.1 × V
OUT
when EN rises from
0 V to V
IN
70 μs
THERMAL SHUTDOWN 3.2 V ≤ V
IN
≤ 15 V
Thermal Shutdown Threshold TS
SD
T
J
rising 150 °C
Thermal Shutdown Hysteresis TS
SD-HYS
15 °C