Datasheet

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Dual 3 MHz, 800 mA Buck

Regulators with Two 300 mA LDOs

Data Sheet

ADP5033

Rev. F Document Feedback

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FEATURES

Main input voltage range: 2.3 V to 5.5 V

Two 800 mA buck regulators and two 300 mA LDOs

Tiny, 16-ball, 2 mm × 2 mm WLCSP package

Regulator accuracy: ±1.8%

Factory programmable VOUTx

3 MHz buck operation with forced PWM and auto PWM/PSM

modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO1/LDO2: output voltage range from 0.8 V to 5.2 V

LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V

LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices

GENERAL DESCRIPTION

The ADP5033 combines two high performance buck regulators

and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm ×

2 mm WLCSP to meet demanding performance and board

space requirements.

The high switching frequency of the buck regulators enables tiny

multilayer external components and minimizes the board space.

When the MODE pin is set high, the buck regulators operate in

forced PWM mode. When the MODE pin is set low, the buck

regulators operate in PWM mode when the load current is above

a predefined threshold. When the load current falls below a

predefined threshold, the regulator operates in power save

mode (PSM), improving the light load efficiency.

The two bucks operate out of phase to reduce the input capacitor

requirement and noise.

The low quiescent current, low dropout voltage, and wide input

voltage range of the ADP5033 LDO extend the battery life of

portable devices. The ADP5033 LDOs maintain power supply

rejection greater than 60 dB for frequencies as high as 10 kHz

while operating with a low headroom voltage.

The regulators in the ADP5033 are activated by the ENA and ENB

pins. The specific channels controlled by ENA and ENB are set

by factory programming. A high voltage level applied to the enable

pins activates the regulators. The default output voltages are

factory programmable and can be set to a wide range of options.

Table 1. Family Models

Model Channels

Maximum

Current Package

ADP5023 2 Buck, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10)

ADP5024 2 Buck, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10)

ADP5034 2 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10),

TSSOP (RE-28-1)

ADP5037 2 Buck, 2 LDOs 800 mA,

300 mA

LFCSP (CP-24-10)

ADP5033 2 Buck, 2 LDOs

with 2 EN pins

800 mA,

300 mA

WLCSP (CB-16-8)

ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10)

ADP5041 1 Buck, 2 LDOs w/

Supervisory,

Watchdog, Manual

Reset

1.2 A, 300 mA LFCSP (CP-20-10)

TYPICAL APPLICATION CIRCUIT

VIN1

2.3V TO 5.5V

SW1

VOUT1

PGND1

MODE

10µF

L1 1µH

BUCK1

4.7µF

VIN2

AGND

BUCK2

SW2

VOUT2

PGND2

10µF

L2 1µH

VOUT3

1µF

VOUT4

1µF

VIN3

1µF

1.7V TO 5.5V

LDO1

(ANALOG)

VIN4

1µF

ADP5033

ENA

ACTIV. AND

UVLO

ENB

OFF

PSM/PWM

PWM

EN1

EN2

EN3

EN4

LDO2

(DIGITAL)

EN2

EN3

EN4

MODE

VOUT1 @

800mA

VOUT2 @

800mA

VOUT3 @

300mA

VOUT4 @

300mA

09788-001

Figure 1.

Summary of content (28 pages)

PAGE 1
Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs ADP5033 Data Sheet FEATURES predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. Main input voltage range: 2.3 V to 5.5 V Two 800 mA buck regulators and two 300 mA LDOs Tiny, 16-ball, 2 mm × 2 mm WLCSP package Regulator accuracy: ±1.8% Factory programmable VOUTx 3 MHz buck operation with forced PWM and auto PWM/PSM modes BUCK1/BUCK2: output voltage range from 0.8 V to 3.
PAGE 2
ADP5033 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Power Management Unit........................................................... 15 General Description ..............................................................
PAGE 3
Data Sheet ADP5033 SPECIFICATIONS GENERAL SPECIFICATIONS VIN1 = VIN2 = VIN3 = VIN4 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2.
PAGE 4
ADP5033 Data Sheet BUCK1 AND BUCK2 SPECIFICATIONS VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 3.
PAGE 5
Data Sheet Parameter DROPOUT VOLTAGE 4 CURRENT-LIMIT THRESHOLD 5 ACTIVE PULL-DOWN POWER SUPPLY REJECTION RATIO Regulator LDO1 ADP5033 Symbol VDROPOUT ILIMIT3, ILIMIT4 RPDWN-L PSRR Regulator LDO2 Test Conditions/Comments VOUT3 = VOUT4 = 5.2 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 3.3 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 2.5 V, IOUT3 = IOUT4 = 300 mA VOUT3 = VOUT4 = 1.8 V, IOUT3 = IOUT4 = 300 mA Min Channel disabled Typ 50 65 85 165 600 600 10 kHz, VIN3 = 3.3 V, VOUT3 = 2.
PAGE 6
ADP5033 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter VIN1 to AGND VIN2 to VIN1 PGND1, PGND2 to AGND VIN3, VIN4, VOUT1, VOUT2, ENA, ENB, MODE to AGND VOUT3 to AGND VOUT4 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.
PAGE 7
Data Sheet ADP5033 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 2 1 3 4 VOUT3 VIN3 VIN4 VOUT4 AGND MODE ENA A ENB B VIN1 VOUT1 VOUT2 VIN2 C PGND1 SW1 SW2 PGND2 TOP VIEW (BALL SIDE DOWN) Not to Scale 09788-002 D Figure 2. Pin Configuration—View from the Top of the Die Table 8. Pin Function Descriptions Pin No.
PAGE 8
ADP5033 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN1= VIN2 = VIN3= VIN4 = 3.6 V, TA = 25°C, unless otherwise noted. 3.310 140 3.305 –40°C 3.300 100 +25°C VOUT (V) 3.295 80 3.290 60 3.285 40 3.280 20 3.275 2.8 3.3 3.8 4.3 4.8 09788-139 3.270 0 2.3 5.3 INPUT VOLTAGE (V) +85°C 0 01 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IOUT (A) 09788-225 QUIESCENT CURRENT (µA) 120 Figure 6. BUCK1 Load Regulation Across Temperature, VIN = 4.2 V, VOUT1 = 3.3 V, PWM Mode Figure 3.
PAGE 9
ADP5033 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 40 VIN = 3.9V VIN = 4.2V VIN = 5.5V 0 10 100 1000 ILOAD (mA) 0 0.001 1 Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 60 50 40 30 30 VIN = 2.3V VIN = 3.6V VIN = 4.2V VIN = 5.5V 20 20 VIN = 3.9V 10 10 VIN = 4.2V VIN = 5.5V 0.1 1 0 0.001 09788-039 0.01 IOUT (A) 0.01 0.1 1 IOUT (A) Figure 13. BUCK1 Efficiency vs.
PAGE 10
ADP5033 Data Sheet 100 3.3 90 3.2 80 3.1 FREQUENCY (MHz) EFFICIENCY (%) 70 60 50 40 30 3.0 2.9 2.8 2.7 20 0.1 1 IOUT (A) 2.5 0 0.2 0.4 0.6 IOUT (A) 0.8 1.0 1.2 09788-040 0.01 09788-062 0 0.001 TA = +25°C TA = –40°C TA = +85°C 2.6 +25°C +85°C –40°C 10 Figure 18. BUCK2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature, VIN1 = 3.9 V, VOUT1 = 3.
PAGE 11
Data Sheet ADP5033 T T VOUT 1 VIN ISW VOUT 2 1 SW SW 4 3 M 400ns A CH2 220mA T 28.40% CH1 50.0mV CH3 1.00V 09788-027 CH2 500mA Ω CH4 2.00V CH1 50mV Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode CH4 2.00V M 1.00ms A CH3 4.80V T 30.40% 09788-013 4 Figure 24. BUCK2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T SW VOUT 1 4 ISW VOUT 2 1 SW IOUT M 400ns A CH2 220mA T 28.40% 09788-026 CH2 500mA Ω CH4 2.
PAGE 12
ADP5033 Data Sheet T SW EN 4 2 VOUT 1 VOUT 3 2 IIN CH1 50.0mV CH2 200mA Ω CH4 5.00V M 20.0µs A CH2 408mA T 20.40% 09788-017 1 CH1 100MA CH3 1.00V Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Auto Mode M 40.0µs CH2 5.00V A CH2 T 159.400µs 4.20V 09788-022 IOUT Figure 30. LDO Startup, VOUT3 = 1.8 V 3.304 T 3.303 SW 3.302 4 VIN = 5.5V VOUT (V) 3.301 VOUT 1 3.300 VIN = 4.2V 3.299 VIN = 3.8V 3.298 3.297 IOUT 3.
PAGE 13
Data Sheet 3.0 IOUT = 10mA IOUT = 100µA T IOUT = 1mA IOUT = 100mA IOUT = 150mA IOUT = 300mA 2.5 2.0 VOUT (V) ADP5033 VIN 1.5 VOUT 2 1 1.0 0.5 CH1 20.0mV CH3 1.00V 09788-234 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VIN (V) M 100µs T 28.40% 4.80V Figure 36. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V, VOUT3 = 2.8 V Figure 33. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V 60 50 VIN = 5V 45 55 VIN = 3.
PAGE 14
ADP5033 Data Sheet 0 –10 –20 –20 –40 –40 PSRR (dB) PSRR (dB) –30 0 100µA 1mA 10mA 50mA 100mA 150mA –50 –60 100µA 1mA 10mA 50mA 100mA 150mA –60 –80 –70 –80 –100 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –120 10 09788-050 Figure 39. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.
PAGE 15
Data Sheet ADP5033 THEORY OF OPERATION VOUT1 GM ERROR AMP VDDA ENBK1 VOUT2 75Ω 75Ω ENBK2 ADP5033 GM ERROR AMP PWM COMP PWM COMP SOFT START VIN1 VIN2 SOFT START ILIMIT ILIMIT PSM COMP LOW CURRENT PSM COMP PWM/ PSM CONTROL BUCK1 PWM/ PSM CONTROL BUCK2 LOW CURRENT SW2 SW1 DRIVER AND ANTISHOOT THROUGH OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCKOUT OPMODE SEL B THERMAL SHUTDOWN PGND1 PGND2 MODE2 Y ENLDO1 600Ω A MODE ENBK1 ENABLE AND MODE CONTROL ENB LDO
PAGE 16
ADP5033 Data Sheet Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VIN1 drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VIN1 rises above the UVLO threshold, the part is enabled once more.
PAGE 17
Data Sheet ADP5033 PSM Current Limit The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enters PSM, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode.
PAGE 18
ADP5033 Data Sheet APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Output Capacitor Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1. Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias.
PAGE 19
Data Sheet ADP5033 The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: VRIPPLE = I RIPPLE VIN ≈ 8 × f SW × COUT (2π × f SW )2 × L × COUT Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT ≤ VRIPPLE I RIPPLE The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum o
PAGE 20
ADP5033 Data Sheet Input Capacitor Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: VOUT (VIN − VOUT ) VIN To minimize supply noise, place the input capacitor as close to the VINx pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended.
PAGE 21
Data Sheet ADP5033 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5033 is a highly efficient micropower management unit (µPMU), and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5033 turns off all the regulators, allowing the device to cool down.
PAGE 22
ADP5033 Data Sheet Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance.
PAGE 23
Data Sheet ADP5033 PCB LAYOUT GUIDELINES Poor layout can affect ADP5033 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: • • • • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks.
PAGE 24
ADP5033 Data Sheet TYPICAL APPLICATION SCHEMATIC ADP5033 VCORE PROCESSOR L1 1µH SW1 VIN1 VCORE VOUT1 C1 4.7µF BUCK1 PGND1 C5 4.7µF ALWAYS ON ENA VIN: 2.3V TO 5.5V ACT ENB BK1 BK2 LD1 LD2 MODE VIN2 SW2 C2 4.7µF BUCK2 L2 1µH FROM VCORE (1.7V MIN) VIN3 LDO1 VIN4 LDO2 C6 4.7µF VOUT3 C7 1µF C3 1µF C4 1µF VIO VOUT2 PGND2 FROM VIO (1.7V MIN) GPIO VIO VOUT4 C8 1µF ANALOG SUBSYSTEM VANA VDIG AGND Figure 47. Processor System Power Management with PSM/PWM Control Rev.
PAGE 25
Data Sheet ADP5033 OUTLINE DIMENSIONS 2.040 2.000 SQ 1.960 4 3 2 1 A BALL A1 IDENTIFIER B 1.50 REF C D 0.50 REF SEATING PLANE BOTTOM VIEW (BALL SIDE UP) SIDE VIEW 0.390 0.360 0.330 COPLANARITY 0.04 0.360 0.320 0.280 0.270 0.240 0.210 Figure 48. 16-Ball Wafer Level Chip Scale Package [WLCSP] Back-Coating Included (CB-16-8) Dimensions shown in millimeters Rev. F | Page 25 of 28 10-19-2012-B 0.660 0.600 0.
PAGE 26
ADP5033 Data Sheet ORDERING GUIDE Model 1 ADP5033ACBZ-1-R7 Temperature Range −40°C to +125°C ADP5033ACBZ-2-R7 −40°C to +125°C ADP5033ACBZ-3-R7 −40°C to +125°C ADP5033ACBZ-4-R7 −40°C to +125°C ADP5033ACBZ-5-R7 −40°C to +125°C ADP5033ACBZ-6-R7 −40°C to +125°C Output Voltage (V) 2 VOUT1: 1.2 V, VOUT2: 3.3 V, VOUT3: 2.8 V, VOUT4: 1.8 V VOUT1: 1.8 V, VOUT2: 2.8 V, VOUT3: 2.8 V, VOUT4: 3.0 V VOUT1: 3.0 V, VOUT2: 1.2 V, VOUT3: 1.8 V, VOUT4: 3.0 V VOUT1: 0.9 V, VOUT2: 0.9 V, VOUT3: 3.0 V, VOUT4: 2.
PAGE 27
Data Sheet ADP5033 NOTES Rev.