Datasheet

Data Sheet ADP5033
Rev. F | Page 17 of 28
PSM
The bucks smoothly transition to PSM operation when the load
current decreases below the PSM current threshold. When either of
the bucks enters PSM, an offset is induced in the PWM regulation
level, which makes the output voltage rise. When the output
voltage reaches a level approximately 1.5% above the PWM
regulation level, PWM operation is turned off. At this point,
both power switches are off, and the buck enters an idle mode.
The output capacitor discharges until the output voltage falls to
the PWM regulation voltage, at which point the device drives
the inductor to make the output voltage rise again to the upper
threshold. This process is repeated while the load current is
below the PSM current threshold.
The ADP5033 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces both bucks to operate in PWM mode. A logic level
low sets the bucks to operate in auto PSM/PWM.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The bucks employ a
scheme that enables this current to remain accurately controlled,
independent of input and output voltage levels. This scheme
also ensures that there is very little hysteresis between the PSM
current threshold for entry to and exit from the PSM. The PSM
current threshold is optimized for excellent efficiency over all
load currents.
Oscillator/Phasing of Inductor Switching
The ADP5033 ensures that both bucks operate at the same
switching frequency when both bucks are in PWM mode.
Additionally, the ADP5033 ensures that when both bucks are in
PWM mode, they operate out of phase, whereby the BUCK2 PFET
starts conducting exactly half a clock period after the BUCK1
PFET starts conducting.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possibility
of a hard short at the output, the switching frequency is reduced
to half the internal oscillator frequency. The reduction in the
switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the output
voltage in a controlled manner upon startup, thereby limiting
the inrush current. This prevents possible input voltage drops
when a battery or a high impedance power source is connected
to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the output.
The negative current limit prevents the inductor current from
reversing direction and flowing out of the load.
100% Duty Operation
With a dropin input voltage or with an increase in load current,
the buck may reach a limit where, even with the PFET switch on
100% of the time, the output voltage drops below the desired
output voltage. At this limit, the buck transitions to a mode where
the PFET switch stays on 100% of the time. When the input
conditions change again and the required duty cycle falls, the
buck immediately restarts PWM regulation without allowing
overshoot on the output voltage.
Active Pull-Downs
All regulators have optional, factory programmable, active pull-
down resistors discharging the respective output capacitors when
the regulators are disabled by the ENx pins or by a faulty condition.
The pull-down resistors are connected between VOUTx and
AGND. Active pull-downs are disabled when the regulators are
turned on. The typical value of the pull-down resistor is 600 Ω for
the LDOs and 75 Ω for the bucks. Figure 44 shows the activation
timings for the active pull-down during regulator activation and
deactivation.
LDO1 AND LDO2
The ADP5033 contains two LDOs with low quiescent current
and low dropout voltage, and provides up to 300 mA of output
current. Drawing a low 25 μA quiescent current (typical) at no load
makes the LDO ideal for battery-operated portable equipment.
Each LDO operates with an input voltage of 1.7 V to 5.5 V. The
wide operating range makes these LDOs suitable for cascading
configurations where the LDO supply voltage is provided from
one of the buck regulators.
Each LDO also provides high power supply rejection ratio (PSRR),
low output noise, and excellent line and load transient response
with just a small 1 µF ceramic input and output capacitor.
LDO1 is optimized to supply analog circuits because it offers
better noise performance compared to LDO2. LDO1 should be
used in applications where noise performance is critical.