Datasheet

ADP5033 Data Sheet
Rev. F | Page 20 of 28
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
IN
OUT
IN
OUT
MAXLOAD
CIN
V
VVV
II
)(
)(
−
≥
To minimize supply noise, place the input capacitor as close to
the VINx pin of the buck as possible. As with the output capacitor,
a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. A list of suggested capacitors is shown in
Table 11.
Table 11. Suggested 4.7 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating (V)
Murata X5R GRM188R60J475ME19D 0402 6.3
Taiyo Yuden X5R JMK107BJ475 0402 6.3
Panasonic X5R ECJ-0EB0J475M 0402 6.3
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5033 LDOs are designed for operation with small,
space-saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken with the ESR value. The
ESR of the output capacitor affects the stability of the LDO control
loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or
less is recommended to ensure the stability of the ADP5033.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP5033 to large changes
in load current.
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 µF of output
capacitance is required, increase the input capacitor to match it.
Table 12. Suggested 1.0 μF Capacitors
Vendor Type Model
Case
Size
Voltage
Rating (V)
Murata X5R GRM155B30J105K 0402 6.3
TDK X5R C1005JB0J105KT 0402 6.3
Panasonic
X5R
ECJ0EB0J105K
0402
6.3
Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5033 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
LDO because of their poor temperature and dc bias characteristics.
Figure 46 depicts the capacitance vs. voltage bias characteristic
of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5 6
DC BIAS VOLTAGE (V)
CAPACITANCE (µF)
09788-006
Figure 46. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capacitance
accounting for capacitor variation over temperature, component
tolerance, and voltage:
C
EFF
= C
BIAS
× (1 − TEMPCO) × (1 − TOL)
where:
C
BIAS
is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C
BIAS
is 0.85 μF at 1.8 V, as shown in Figure 46.
Substituting these values into the following equation,
C
EFF
= 0.85 μF × (1 − 0.15) × (1 − 0.1) ≈ 0.65 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5033, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.