Datasheet

ADP5033 Data Sheet
Rev. F | Page 24 of 28
TYPICAL APPLICATION SCHEMATIC
VIN1
ENA
VIN:
2.3V TO 5.5V
SW1
VOUT1
VCORE
VCORE
VIO
VIO
GPIO
PGND1
MODE
C5
4.7µF
L1 1µH
BUCK1
ACT
C2
4.7µF
C1
4.7µF
VIN2
ENB
AGND
BUCK2
ON
OFF
SW2
VOUT2
PGND2
C6
4.7µF
L2 1µH
VOUT3
C7
1µF
VOUT4
C8
1µF
PROCESSOR
VANA
VDIG
ANALOG
SUBSYSTEM
VIN3
C3
1µF
FROM VIO
(1.7V MIN)
LDO1
VIN4
C4
1µF
FROM VCORE
(1.7V MIN)
ADP5033
ALWAYS ON
BK1
BK2
LD1
LD2
LDO2
09788-152
Figure 47. Processor System Power Management with PSM/PWM Control