Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - linear/switching voltage regulator Arbitrary function TSSOP 28 EP

Dual 3 MHz, 1200 mA Buck

Regulators with Two 300 mA LDOs

Data Sheet

ADP5034

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Main input voltage range: 2.3 V to 5.5 V

Two 1200 mA buck regulators and two 300 mA LDOs

24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package

Regulator accuracy: ±1.8%

Factory programmable or external adjustable VOUTx

3 MHz buck operation with forced PWM and auto PWM/PSM

modes

BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V

LDO1/LDO2: output voltage range from 0.8 V to 5.2 V

LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V

LDO1/LDO2: high PSRR and low output noise

APPLICATIONS

Power for processors, ASICS, FPGAs, and RF chipsets

Portable instrumentation and medical devices

Space constrained devices

GENERAL DESCRIPTION

The ADP5034 combines two high performance buck regulators

and two low dropout (LDO) regulators. It is available in either a

24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package.

The high switching frequency of the buck regulators enables tiny

multilayer external components and minimizes the board space.

When the MODE pin is set to high, the buck regulators operate in

forced PWM mode. When the MODE pin is set to low, the buck

regulators operate in PWM mode when the load is above a pre-

defined threshold. When the load current falls below a predefined

threshold, the regulator operates in power save mode (PSM),

improving the light load efficiency.

Table 1. Family Models

Model Channels

Maximum

Current

Package

ADP5023 2 Buck,1 LDO

800 mA,

300 mA

LFCSP (CP-24-10)

ADP5024 2 Buck,1 LDO

1.2 A,

300 mA

LFCSP (CP-24-10)

ADP5034 2 Buck,2 LDOs

1.2 A,

300 mA

LFCSP (CP-24-10),

TSSOP (RE-28-1)

ADP5037 2 Buck,2 LDOs

800 mA,

300 mA

LFCSP (CP-24-10)

ADP5033

2 Buck,2 LDOs with

2 EN pins

800 mA,

300 mA

WLCSP (CB-16-8)

The two bucks operate out of phase to reduce the input capaci-

tor requirement. The low quiescent current, low dropout voltage,

and wide input voltage range of the ADP5034 LDOs extend the

battery life of portable devices. The ADP5034 LDOs maintain

power supply rejection greater than 60 dB for frequencies as

high as 10 kHz while operating with a low headroom voltage.

Regulators in the ADP5034 are activated through dedicated

enable pins. The default output voltages can be externally set in

the adjustable version, or factory programmable to a wide range

of preset values in the fixed voltage version.

TYPICAL APPLICATION CIRCUIT

09703-001

VIN1

VIN3

EN1

PWM

PSM/PWM

2.3V TO

5.5V

SW1

FB1

VOUT1

PGND1

MODE

10µF

OUT1

1200mA

OUT2

1200mA

OUT3

300mA

OUT4

300mA

L1 1µH

EN1

BUCK1

MODE

1µF

4.7µF

AVIN

0.1µF

1µF

VIN2

EN2

AGND

EN2

BUCK2

MODE

EN3

1.7V TO

5.5V

EN4

VIN4

OFF

EN3

LDO1

(ANALOG)

ADP5034

HOUSEKEEPING

SW2

FB2

VOUT2

PGND2

10µF

L2 1µH

FB3

VOUT3

1µF

FB4

VOUT4

1µF

EN4

LDO2

(DIGITAL)

Figure 1.

Summary of content (28 pages)

PAGE 1
Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs ADP5034 Data Sheet FEATURES regulators operate in PWM mode when the load is above a predefined threshold. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. Main input voltage range: 2.3 V to 5.5 V Two 1200 mA buck regulators and two 300 mA LDOs 24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package Regulator accuracy: ±1.
PAGE 2
ADP5034 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Power Management Unit........................................................... 16 General Description ..............................................................
PAGE 3
Data Sheet ADP5034 REVISION HISTORY 5/13—Rev. D to Rev. E Added Table 1; Renumbered Sequentially ..................................... 1 Changes to Figure 1........................................................................... 1 Changes to NC Pin Description ...................................................... 8 Changes to Figure 49 ......................................................................19 Changes to Figure 51 ......................................................................
PAGE 4
ADP5034 Data Sheet SPECIFICATIONS GENERAL SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; VIN3 = VIN4 = 1.7 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2.
PAGE 5
Data Sheet ADP5034 BUCK1 AND BUCK2 SPECIFICATIONS VAVIN = VIN1 = VIN2 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 3.
PAGE 6
ADP5034 Parameter OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation 3 VOLTAGE FEEDBACK DROPOUT VOLTAGE 4 CURRENT-LIMIT THRESHOLD 5 ACTIVE PULL-DOWN OUTPUT NOISE Regulator LDO1 Regulator LDO2 POWER SUPPLY REJECTION RATIO Regulator LDO1 Data Sheet Symbol Test Conditions/Comments Min ΔVOUT3/VOUT3, ΔVOUT4/VOUT4 (ΔVOUT3/VOUT3)/ΔVIN3, (ΔVOUT4/VOUT4)/ΔVIN4 (ΔVOUT3/VOUT3)/ΔIOUT3, (ΔVOUT4/VOUT4)/ΔIOUT4 100 µA < IOUT3 < 300 mA, 100 µA < IOUT4 < 300 mA IOUT3 = IOUT4 = 1 mA Max Unit
PAGE 7
Data Sheet ADP5034 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVIN to AGND VIN1, VIN2 to AVIN PGND1, PGND2 to AGND VIN3, VIN4, VOUT1, VOUT2, FB1, FB2, FB3, FB4, EN1, EN2, EN3, EN4, MODE to AGND VOUT3 to AGND VOUT4 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN3 + 0.3 V) −0.3 V to (VIN4 + 0.3 V) −0.3 V to (VIN1 + 0.
PAGE 8
ADP5034 Data Sheet 1 2 3 4 5 6 PIN 1 INDICATOR ADP5034 TOP VIEW (Not to Scale) 18 17 16 15 14 13 AGND AVIN VIN1 SW1 PGND1 MODE EN2 FB2 VOUT2 VOUT1 FB1 EN1 7 8 9 10 11 12 FB4 EN4 VIN2 SW2 PGND2 NC 28 VIN3 27 VOUT3 VOUT4 3 26 FB3 NC 4 25 NC FB4 5 ADP5034 24 AGND EN4 6 TOP VIEW (Not to Scale) 23 AVIN VIN2 7 22 VIN1 SW2 8 21 SW1 PGND2 9 20 PGND1 NC 10 19 MODE NC 11 18 NC EN2 12 17 EN1 FB2 13 16 FB1 VOUT2 14 15 VOUT1 NOTES 1. NC = NOT INTERNALLY CONNECTED. 2.
PAGE 9
Data Sheet ADP5034 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3= VIN4 = 3.6 V, TA = 25°C, unless otherwise noted. 3.320 3.315 3.310 120 TA = –40°C 3.305 100 VOUT (V) QUIESCENT CURRENT (µA) 140 80 60 3.300 TA = +25°C 3.295 3.290 3.285 TA = +85°C 40 3.280 20 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 3.270 0.2 0 0.4 0.6 0.8 1.0 1.2 IOUT (A) Figure 4. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.
PAGE 10
ADP5034 100 VIN = 3.9V 80 80 VIN = 4.2V VIN = 2.3V 70 50 40 20 20 10 10 0 0.001 09703-104 0.1 1 ILOAD (A) 100 90 90 80 80 VIN = 5.5V 70 EFFICIENCY(%) VIN = 3.9V 60 50 40 60 50 VIN = 5.5V VIN = 2.3V VIN = 3.6V 40 20 20 VIN = 4.2V 10 0.01 1 0.1 IOUT (A) 0 0.001 09703-018 0 0.001 100 90 90 80 80 VIN = 2.3V 70 VIN = 5.5V EFFICIENCY (%) VIN = 4.2V VIN = 3.6V 50 40 20 10 10 0 0.001 09703-020 IOUT (A) VIN = 5.5V 40 20 1 VIN = 2.3V 50 30 0.1 1 VIN = 3.
PAGE 11
Data Sheet ADP5034 100 3.3 –40°C 90 3.2 +25°C SCOPE FREQUENCY (MHz) 80 EFFICIENCY (%) 70 60 50 40 30 3.1 3.0 +85°C 2.9 2.8 2.7 20 +25°C +85°C –40°C 2.6 0.1 0.01 1 IOUT (A) 0 0.2 0.4 0.6 0.8 1.0 09703-031 2.5 0 0.001 09703-028 10 1.2 IOUT (A) Figure 19. BUCK2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode Figure 16. BUCK1 Efficiency vs. Load Current, Across Temperature, VIN = 3.9 V, VOUT1 = 3.
PAGE 12
ADP5034 Data Sheet T T VOUT 1 VIN ISW VOUT 2 1 SW SW 4 3 CH2 500mA Ω M 400ns A CH2 BW CH4 2.00V T 28.40% BW 220mA CH1 50.0mV CH3 1.00V BW BW M 1.00ms CH4 2.00V A CH3 4.80V BW T 30.40% Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode 09703-041 CH1 50mV 09703-053 4 Figure 25. BUCK2 Response to Line Transient, VIN2 = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T SW VOUT 1 4 ISW 2 VOUT 1 SW IOUT 4 M 400ns A CH2 CH2 500mA Ω BW CH4 2.00V T 28.
PAGE 13
Data Sheet ADP5034 T SW EN 4 2 VOUT 1 VOUT 3 IOUT IIN 2 BW CH2 200mA Ω CH4 5.00V BW M 20.0µs A CH2 408mA BW T 20.40% CH1 100mA CH2 5V CH3 1V M40µs 2.50GS/s T 159.40µs A CH2 4.20V 09703-105 CH1 50.0mV 09703-045 1 Figure 31. LDO Startup, VOUT3 = 1.8 V Figure 28. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Auto Mode 3.3160 T 3.3155 SW 3.3150 4 VIN = 5.5V VOUT (V) 3.3145 VOUT 1 3.3140 3.3135 VIN = 4.2V 3.3130 3.3125 IOUT VIN = 3.8V 3.
PAGE 14
ADP5034 Data Sheet 250 50 45 200 40 +125°C GROUND CURRENT (µA) RDSON (mΩ) +25°C 150 –40°C 100 35 30 25 20 15 50 10 3.3 3.8 4.3 4.8 5.3 INPUT VOLTAGE (V) 0 09703-038 2.8 0 0.10 0.05 0.15 0.20 09703-036 5 0 2.3 0.25 LOAD CURRENT (A) Figure 34. LFCSP PMOS RDSON vs. Input Voltage Across Temperature Figure 37. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 1.802 T 1.801 TA = –40°C 1.800 IOUT VOUT (V) 1.799 2 1.798 TA = +25°C 1.797 1.796 1 VOUT 1.
PAGE 15
Data Sheet ADP5034 60 0 VIN = 5V 55 –20 VIN = 3.3V –40 PSRR (dB) 45 40 –60 –80 35 –100 30 0.01 0.1 1 10 –120 10 09703-055 25 0.001 100 ILOAD (mA) Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 43. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V 0 65 VIN = 5V 60 –20 VIN = 3.
PAGE 16
ADP5034 Data Sheet THEORY OF OPERATION VOUT1 FB1 FB2 VOUT2 GM ERROR AMP AVIN ENBK1 75Ω 75Ω ENBK2 GM ERROR AMP PWM COMP PWM COMP VIN1 SOFT START SOFT START PSM COMP PSM COMP VIN2 ILIMIT ILIMIT LOW CURRENT PWM/ PSM CONTROL BUCK2 PWM/ PSM CONTROL BUCK1 LOW CURRENT SW2 SW1 OSCILLATOR DRIVER AND ANTISHOOT THROUGH DRIVER AND OP ANTISHOOT MODE THROUGH SYSTEM UNDERVOLTAGE LOCKOUT SEL THERMAL SHUTDOWN PGND1 Y B PGND2 MODE2 ENLDO2 600Ω A MODE EN2 EN3 EN4 ENBK1 ENABLE AND MODE CONTROL
PAGE 17
Data Sheet ADP5034 Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off all the regulators. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130°C.
PAGE 18
ADP5034 Data Sheet BUCK1 AND BUCK2 The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. The buck output voltage is set through external resistor dividers, shown in Figure 48 for BUCK1. The output voltage can optionally be factory programmed to default values as indicated in the Ordering Guide section. In this event, R1 and R2 are not needed, and FB1 can be left unconnected.
PAGE 19
Data Sheet ADP5034 Active Pull-Downs All regulators have optional, factory programmable, active pulldown resistors discharging the respective output capacitors when the regulators are disabled. The pull-down resistors are connected between VOUTx and AGND. Active pull-downs are disabled when the regulators are turned on. The typical value of the pull-down resistor is 600 Ω for the LDOs and 75 Ω for the bucks.
PAGE 20
ADP5034 Data Sheet APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors For the adjustable model, referring to Figure 50 the total combined resistance for R1 and R2 is not to exceed 400 kΩ.
PAGE 21
Data Sheet ADP5034 To minimize supply noise, place the input capacitor as close as possible to the VINx pin of the buck. As with the output capacitor, a low ESR capacitor is recommended. The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF.
PAGE 22
ADP5034 Data Sheet LDO EXTERNAL COMPONENT SELECTION 1.2 Feedback Resistors The ADP5034 LDOs are designed for operation with small, spacesaving ceramic capacitors, but function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure that stability of the ADP5034.
PAGE 23
Data Sheet ADP5034 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5034 is a highly efficient µPMU, and, in most cases, the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 150°C, the ADP5034 turns off all the regulators, allowing the device to cool down.
PAGE 24
ADP5034 Data Sheet Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the P-MOSFET gate capacitance. CGATE-N is the N-MOSFET gate capacitance.
PAGE 25
Data Sheet ADP5034 PCB LAYOUT GUIDELINES Poor layout can affect ADP5034 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to the UG-271 and UG-439 user guide. • • • • • Place the inductor, input capacitor, and output capacitor close to the IC using short tracks.
PAGE 26
ADP5034 Data Sheet TYPICAL APPLICATION SCHEMATICS AVIN CAVIN 0.1µF HOUSEKEEPING VOUT1 VIN1 2.3V TO 5.5V SW1 C1 4.7µF ON OFF BUCK1 EN1 EN1 L1 1µH C5 10µF PGND1 MODE PWM MODE MODE SW2 C2 4.7µF BUCK2 EN2 ON EN3 EN2 EN3 VIN3 1.7V TO 5.
PAGE 27
Data Sheet ADP5034 OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 13 12 2.20 2.10 SQ 2.00 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-11-2012-A COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. Figure 55.
PAGE 28
ADP5034 Data Sheet ORDERING GUIDE Model 1 ADP5034ACPZ-R2 Temperature Range −40°C to +125°C Output Voltage (V) 2 Adjustable UVLO 3 Low ADP5034ACPZ-R7 −40°C to +125°C Adjustable Low ADP5034ACPZ-1-R7 −40°C to +125°C Low ADP5034ACPZ-2-R7 −40°C to +125°C VOUT1 = 1.2 V VOUT2 = 3.3 V VOUT3 = 2.8 V VOUT4 = 1.