Datasheet

Data Sheet ADP5034
Rev. E | Page 13 of 28
4
2
T
1
CH1 50.0mV
CH4 5.00V
M 20.0µs A CH2 408mA
T 20.40%
B
W
CH2 200mA Ω
B
W
B
W
VOUT
I
OUT
SW
09703-045
Figure 28. BUCK1 Response to Load Transient, I
OUT1
from 20 mA to 180 mA,
V
OUT1
= 3.3 V, Auto Mode
4
2
T
1
CH1 100mV
CH4
5.00V
M 20.0µs A CH2 88.0mA
T 19.20%
B
W
CH2 200mA Ω
B
W
B
W
VOUT
I
OUT
SW
09703-046
Figure 29. BUCK2 Response to Load Transient, I
OUT2
from 20 mA to 180 mA,
V
OUT2
= 1.8 V, Auto Mode
4
1
3
T
2
CH1 5.00V
CH4 5.00V
M 400ns A CH4 1.90V
T 50.00%
B
W
CH2 5.00V
B
W
B
W
CH3 5.00V
B
W
VOUT1
VOUT2
SW1
SW2
09703-060
Figure 30. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
09703-105
CH1 100mA
CH3 1V
CH2 5V
M40µs 2.50GS/s
A CH2 4.20V
1
2
3
T 159.40µs
EN
I
IN
VOUT
Figure 31. LDO Startup, V
OUT3
= 1.8 V
3.3160
3.3110
3.3115
3.3120
3.3125
3.3130
3.3135
3.3140
3.3145
3.3150
3.3155
0 100 20050 150 250 300
V
OUT
(V)
I
OUT
(mA)
09703-106
V
IN
= 3.8V
V
IN
= 4.2V
V
IN
= 5.5V
Figure 32. LDO Load Regulation Across Input Voltage, V
OUT3
= 3.3 V
0
50
100
150
200
250
300
350
400
2.3 2.8 3.3 3.8 4.3 4.8 5.3
RDS
ON
(mΩ)
INPUT VOLTAGE (V)
09703-037
+25°C
+125°C
–40°C
Figure 33. LFCSP NMOS RDS
ON
vs. Input Voltage Across Temperature