Datasheet

ADP5034 Data Sheet
Rev. E | Page 24 of 28
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
IN1
2
× f
SW
(10)
where:
C
GATE -P
is the P-MOSFET gate capacitance.
C
GATE -N
is the N-MOSFET gate capacitance.
For the ADP5034, the total of (C
GATE -P
+ C
GATE -N
) is
approximately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
OUT1
(and from V
OUT1
to ground). The amount of transition
loss is calculated by
P
TRAN
= V
IN1
× I
OUT1
× (t
RISE
+ t
FALL
) × f
SW
(11)
where t
RISE
and t
FALL
are the rise time and the fall time of the
switching node, SW. For the ADP5034, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimat-
ing the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
P
DLDO
= [(V
IN
− V
OUT
) × I
LOAD
] + (V
IN
× I
GND
) (12)
where:
I
LOAD
is the load current of the LDO regulator.
V
IN
and V
OUT
are input and output voltages of the LDO,
respectively.
I
GND
is the ground current of the LDO regulator.
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5034 simplifies to
P
D
= P
DBUCK1
+ P
DBUCK2
+ P
DLDO1
+ P
DLDO2
(13)
JUNCTION TEMPERATURE
In cases where the board temperature, T
A
, is known, the
thermal resistance parameter, θ
JA
, can be used to estimate the
junction temperature rise. T
J
is calculated from T
A
and P
D
using
the formula
T
J
= T
A
+ (P
D
× θ
JA
) (14)
Refer to Table 7 for the thermal resistance values of the LFCSP
and TSSOP packages. A very important factor to consider is
that θ
JA
is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
T
J
= T
C
+ (P
D
× θ
JC
) (15)
where T
C
is the case temperature and θ
JC
is the junction-to-case
thermal resistance provided in Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5034 power
dissipation (P
D
) due to the losses of all channels by using the
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
J
, can be estimated using Equation 14.
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5034 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBF) are highly affected by increas-
ing the junction temperature. Additional information about
product reliability can be found from the ADI Reliability Handbook,
which can be found at
www.analog.com/reliability_handbook.