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Fast Charge Battery Manager with Power

Path and USB Compatibility

Data Sheet

ADP5065

Rev. D Document Feedback

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FEATURES

3 MHz switch mode charger

1.25 A charge current from dedicated charger

Up to 680 mA charging current from 500 mA USB host

Operating input voltage from 4.0 V up to 5.5 V

Tolerant input voltage −0.5 V to +20 V (USB VBUS)

Dead battery isolation FET between battery and

charger output

Battery thermistor input with automatic charger shutdown

for when battery temperature exceeds limits

Compliant with the JEITA Li-Ion battery charging

temperature specification

SYS_EN_OK flag to hold off system turn-on until battery is at

minimum required level for guaranteed system startup

due to minimum battery voltage and/or minimum battery

charge level requirements

EOC programming with C/20, C/10 and specific current level

selection

APPLICATIONS

Digital still cameras

Digital video cameras

Single cell Li-Ion portable equipment

PDA, audio, GPS devices

Mobile phones

FUNCTIONAL BLOCK DIAGRAM

V_WEAK_SET AGND

PGNDx

IIN_EXT

TRK_EXT

SCL

SDA

SYS_ON_OK

CHARGER

CONTROL

BLOCK

3MHz

BUCK

CFILT

VBUS

USB

VINx

PGNDx

ISO_Sx

ISO_Bx

BAT_SNS

THR

SWx

INDUCTOR

SYSTEM

Li-Ion

ADP5065

09370-001

Figure 1.

GENERAL DESCRIPTION

The ADP5065 charger is fully compliant with the USB 2.0,

USB 3.0, and USB Battery Charging Specification 1.1 and

enables charging via the mini USB VBUS pin from a wall

charger, car charger, or USB host port.

The ADP5065 operates from a 4 V to 5.5 V input voltage range

but is tolerant of voltages of up to 20 V. T h is alleviates the

concerns about the USB bus spiking during disconnect or

connect scenarios.

The ADP5065 also features an internal FET between the dc-to-

dc charger output and the battery. This permits battery isolation

and, hence, system powering under a dead battery or no battery

scenario, which allows for immediate system function on

connection to a USB power supply.

Based on the type of USB source, which is detected by an external

USB detection chip, the ADP5065 can be set to apply the correct

current limit for optimal charging and USB compliance.

The ADP5065 comes in a very small and low profile 20-lead

WLCSP (0.5 mm pitch spacing) package.

The overall solution requires only five small, low profile external

components consisting of four ceramic capacitors (one of which

is the battery filter capacitor), one multilayer inductor. In addition

to these components, there is one optional dead battery situation

default setting resistor. This configuration enables a very small

PCB area to provide an integrated and performance enhancing

solution to USB battery charging and power rail provision.

Summary of content (40 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAM 3 MHz switch mode charger 1.25 A charge current from dedicated charger Up to 680 mA charging current from 500 mA USB host Operating input voltage from 4.0 V up to 5.5 V Tolerant input voltage −0.
PAGE 2
ADP5065 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Battery Isolation FET ................................................................. 19 Applications ....................................................................................... 1 Battery Detection ....................................................................... 20 Functional Block Diagram ...................................................
PAGE 3
Data Sheet ADP5065 SPECIFICATIONS −40°C < TJ < 125°C, VIN = 5.0 V, VISO_S > 3.0 V, VHOT < VTHR < VCOLD, VBAT_SNS = 3.6 V, CVIN = 2.2 µF, CDCDC = 22 µF, CBAT = 22 µF, CCFILT = 4.7 µF, LOUT = 1 µH, all registers are at default values, unless otherwise noted. Table 1.
PAGE 4
ADP5065 Data Sheet Parameter BATTERY ISOLATION FET Bump to Bump Resistance Between ISO_Bx and ISO_Sx Bumps Symbol Regulated System Voltage Battery Supplementary Threshold HIGH VOLTAGE BLOCKING FET VINx Input High Voltage Blocking FET On Resistance Current, Suspend Mode Input Voltage Good Threshold Rising Falling Overvoltage Threshold Overvoltage Threshold Hysteresis VINx Transition Timing Minimum Rise Time for VINx from 5 V to 20 V Minimum Fall Time for VINx from 4 V to 0 V THERMAL CONTROL Isothermal Ch
PAGE 5
Data Sheet Parameter BATTERY DETECTION Sink Current Source Current Battery Threshold Low High No Battery Threshold Battery Detection Timer TIMERS Start Charging Delay Timer Trickle Charge Timer Fast Charge Timer Charge Complete Timer Deglitch Timer Watchdog Timer1 Safety Timer Battery Node Short Timer1 LOGIC INPUTS Maximum Voltage on Digital Inputs Maximum Logic Low Input Voltage Minimum Logic High Input Voltage Pull-Down Resistance ADP5065 Symbol Min Typ Max Unit ISINK ISOURCE 13 7 20 10 34 13 m
PAGE 6
ADP5065 Data Sheet I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 3.
PAGE 7
Data Sheet ADP5065 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter VIN1, VIN2 to PGND1, PGND2 All Other Pins to AGND Continuous Drain Current, Battery Supplementary Mode, from ISO_Bx to ISO_Sx TJ ≤ 85°C TJ = 125°C Storage Temperature Range Operating Junction Temperature Range Soldering Conditions θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.5 V to +20 V −0.3 V to +6 V Table 5. Thermal Resistance 2.
PAGE 8
ADP5065 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 2 1 V_WEAK_SET SCL 3 4 THR IIN_EXT A SDA TRK_EXT ISO_B1 ISO_B2 BAT_SNS AGND ISO_S1 ISO_S2 SW1 PGND1 SW2 PGND2 B C VIN1 SYS_ON_OK D VIN2 CFILT TOP VIEW (BALL SIDE DOWN) Not to Scale 09370-003 E Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. D3, E3 D1, E1 D4, E4 Type 1 I/O I/O G Description DC-to-DC Converter Inductor Connection.
PAGE 9
Data Sheet ADP5065 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 VIN INPUT LIMIT 500mA 90 90 VIN INPUT LIMIT 100mA 80 80 70 60 50 40 50 40 30 30 20 20 10 10 2.9 3.3 3.7 4.1 4.5 BATTERY VOLTAGE (V) 0 0.01 09370-004 0 2.5 0.1 1 SYSTEM OUTPUT CURRENT (A) Figure 4. Battery Charger Efficiency vs. Battery Voltage, VIN = 5.0 V Figure 7. System Voltage Efficiency vs. Output Current, VIN = 5.0 V 3.35 4.5 3.34 4.3 3.33 4.
PAGE 10
ADP5065 Data Sheet 4.4 0.7 IISO_B BATTERY VOLTAGE (V) RON RESISTANCE (mΩ) 95 90 85 80 70 2.7 3.0 3.3 3.6 3.9 4.2 BATTERY VOLTAGE (V) 09370-010 75 Figure 10. Battery Isolation FET Resistance vs. Battery Voltage, VIN = 5.0 V, Load Current = 1.0 A 1.6 1.4 VIN CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 0 1 2 3 4 VIN VOLTAGE (V) 5 6 09370-011 0.2 Figure 11. VINx Current vs. VINx Voltage, Suspend Mode (EN_CHG = 0) Rev. D | Page 10 of 40 4.2 0.6 4.0 0.5 IVIN 3.8 0.4 3.6 0.3 3.4 0.
PAGE 11
Data Sheet ADP5065 TEMPERATURE CHARACTERISTICS 1.0 5.70 5.65 0.5 5.60 VTRM ACCURACY (%) VIN OVERVOLTAGE PROTECTION (V) 5.75 5.55 5.50 5.45 5.40 VTRM VTRM VTRM VTRM = 3.50V = 3.80V = 4.20V = 4.42V 0 –0.5 5.35 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) –1.0 –40 09370-013 Figure 13. VINx Overvoltage Protection Rising Threshold vs. Ambient Temperature 60 80 100 120 3.08 SWITCHING FREQUENCY (MHz) 3.300 3.295 3.290 3.285 3.280 3.06 3.04 3.02 3.00 2.98 2.96 2.94 2.
PAGE 12
ADP5065 Data Sheet 0.8 1.0 0.8 0.7 0.6 CHARGE CURRENT (A) 0.7 0.6 0.5 0.4 0.3 0.4 0.3 0.2 0.2 0.1 0 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) 09370-019 0.1 Figure 19. Battery Leakage Current vs. Ambient Temperature 1.32 1.30 1.28 1.26 1.24 1.22 1.20 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) 09370-020 1.18 1.16 –40 0 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) Figure 21. Isothermal Regulation of Charge Current vs. Ambient Temperature, ICHG = 750 mA, VIN = 5.
PAGE 13
Data Sheet ADP5065 TYPICAL WAVEFORMS CIN INRUSH CURRENT T T IISO_B IISO_B 3 3 IVIN IVIN 4 4 VISO_S VISO_S VIN VIN 2 CH1 2.0V CH2 2.0V CH3 200mA CH4 200mA 100µs T 0.00s A CH2 44mA 1 09370-022 1 CH1 2.0V CH2 2.0V CH3 200mA CH4 200mA 100µs T 0.00s A CH3 44mA 09370-025 2 Figure 22. Typical Waveforms, VINx Connect From High Impedance to VBUS, ILIM = 100 mA Figure 25.
PAGE 14
ADP5065 Data Sheet T T VISO_S 2 VISO_S 1 SW 1A 1 ISW IISO_S 0A 4 200µs A CH4 T 600.0µs 250mA Figure 28. System Voltage Load Transient, VIN = 5.0 V, No Battery CH1 2.0V CH2 50.0mV CH4 200mA T 3 VISO_S CH2 2.0V 100µs T 0.00s A CH2 2.76V 09370-029 2 CH3 2.0A W 800ns T –8.00ns A CH1 2.16V Figure 30. Typical Waveforms, Light Load, VIN = 5.0 V, IISO_S = 100 mA CISO_B AND CISO_S INRUSH CURRENT IISO_B B 09370-030 CH1 100mV BW CH4 500mA 09370-028 4 Figure 29.
PAGE 15
Data Sheet ADP5065 THEORY OF OPERATION INTRODUCTION The highly efficient switcher dc-to-dc architecture enables higher charging currents as well as a lower temperature charging operation that results in faster charging times because of the following features: The ADP5065 is fully compliant with the USB 3.0 battery charging specification and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.
PAGE 16
ADP5065 Data Sheet CFILT E2 E1 COIL CURRENT DETECTION SW1 VIN2 SW2 + – 5.42V HV-FET CONTROL D3 E3 VIN LIMIT DC-DC CONTROL – D1 IND_PEAK_INT HIGH VOLTAGE BLOCKING FET VIN1 + TO USB VBUS OR WALL ADAPTER VIN OVERVOLTAGE ISO_S1 TO SYSTEM LOAD C3 3MHz OSC BATTERY ISOLATION FET TRICKLE CURRENT SOURCE + – CHARGE CONTROL EOC ISO_B1 B4 CV-MODE RECHARGE BATTERY DETECTION SINK – AND CONTROL LOGIC SDA B3 ISO_B2 + + B1 I2C INTERFACE SCL CFILT – VIN GOOD A2 C4 + 3.
PAGE 17
Data Sheet ADP5065 The ADP5065 also includes a number of significant features to optimize charging and functionality, including • • • • • • • Thermal regulation for maximum performance. USB host current-limit accuracy: ±5 %. Termination voltage accuracy: ±1 %. Battery thermistor input with automatic charger shutdown in the event that the battery temperature exceeds limits. (Compliant with the JEITA Li-Ion battery charging temperature specification.
PAGE 18
ADP5065 Data Sheet Weak Charge Mode (Constant Current) Fast Charge Mode (Constant Voltage) When the battery voltage exceeds VTRK_DEAD but is less than VWEAK, the charger switches to the intermediate charge mode. As the battery charges, its voltage rises and approaches the termination voltage, VTRM. The ADP5065 charger monitors the voltage on the BAT_SNS pin to determine when charging should end.
PAGE 19
Data Sheet ADP5065 Safety Timer Thermal Shutdown and Thermal Early Warning If the watchdog timer (see the Watchdog Timer section for more information) expires while in charger mode, the ADP5065 charger initiates the safety timer, tSAFE. If the processor has programmed charging parameters by this time, the ILIM is set to the default value. Charging continues for a period of tSAFE, then the charger switches off and sets the CHARGER_STATUS register.
PAGE 20
ADP5065 Data Sheet BATTERY DETECTION Battery (ISO_Bx) Short Detection Battery Level Detection A battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled. The ADP5065 charger features a battery detection mechanism to detect an absent battery. The charger actively sinks and sources current into the ISO_Bx/BAT_SNS node, and voltage vs. time is detected.
PAGE 21
Data Sheet ADP5065 BATTERY PACK TEMPERATURE SENSING Battery Thermistor Input The ADP5065 charger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. The THR pin provides an on and off switching current source, which should be connected directly to the battery pack thermistor terminal. The activation interval of the THR current source is 167 ms.
PAGE 22
ADP5065 Data Sheet EXTERNAL RESISTOR FOR V_WEAK_SET The ADP5065 charger features a VWEAK threshold, which can be used for enabling the main PMU system. When battery voltage at the BAT_SNS pin exceeds the VWEAK level, the ADP5065 pulls down the SYS_ON_OK open-drain flag. The VWEAK threshold can be programmed set either by I2C or by an external resistor connected between the V_WEAK_SET pin and GND. Recommended resistor values for each threshold are listed in Table 13.
PAGE 23
Data Sheet ADP5065 I2C INTERFACE See Figure 34 for an example of the I2C write sequence to a single register. The subaddress content selects which one of the five ADP5065 registers is written to first. The ADP5065 sends an acknowledgement to the master after the 8-bit data byte has been written. The ADP5065 increments the subaddress automatically and starts receiving a data byte to the following register until the master sends an I2C stop as shown in Figure 35.
PAGE 24
ADP5065 Data Sheet CHARGER OPERATIONAL FLOWCHART POWER ON RESET N RESET ALL REGISTERS Y RUN BATTERY DETECTION Y VINOK Y tSTART POWER DOWN N VBAT_SNS < VTRK TRICKLE CHARGE VINOK FAST CHARGE N VINOK N IVIN < ILIM Y WATCHDOG EXPIRED START tSAFE IBUS = 100mA TEMP < TLIM EXPIRED N TFAULT/ BAD BATTERY Y IBUSLIM = HIGH IVIN = ILIM N THERMLIM = HIGH TEMP = TLIM Y tSAFE /tTRK tWD EXPIRED Y EXPIRED WATCHDOG EXPIRED START tSAFE IBUS = 100mA N N RUN BATTERY DETECTION N Y tWD Y N
PAGE 25
Data Sheet ADP5065 I2C REGISTER MAP Table 14. I2C Register Map 1 Register Addr.
PAGE 26
ADP5065 Data Sheet REGISTER BIT DESCRIPTIONS Table 15. Manufacturer and Model ID, Register Address 0x00 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic MANUF[3:0] MODEL[3:0] Access R R Default 0001 1000 Description The 4-bit manufacturer identification bus. The 4-bit model identification bus. Table 16. Silicon Revision, Register Address 0x01 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic Not Used REV[3:0] Access R R Default Description 0101 The 4-bit silicon revision identification bus. Table 17.
PAGE 27
Data Sheet ADP5065 Table 18. Termination Settings, Register Address 0x03 Bit Descriptions Bit No. [7:2] Mnemonic VTRM[5:0] Access R/W Default 100011 = 4.20 V Description Termination voltage programming bus. The values of the float voltage can be programmed as per the following values: 000000 = 3.50 V. 000001 = 3.52 V. 000010 = 3.54 V. 000011 = 3.56 V. 000100 = 3.58 V. 000101 = 3.60 V. 000110 = 3.62 V. 000111 = 3.64 V. 001000 = 3.66 V. 001001 = 3.68 V. 001010 = 3.70 V. 001011 = 3.72 V. 001100 = 3.74 V.
PAGE 28
ADP5065 Bit No. [1:0] Mnemonic IEND[1:0] Data Sheet Access R/W Default 01 = 52.5 mA Description Termination current programming bus. The values of the termination current can be programmed as per the following values: 00 = 32.5 mA. 01 = 52.5 mA. 10 = 72.5 mA. 11 = 92.5 mA. Table 19. Charging Current, Register Address 0x04 Bit Descriptions Bit No. 7 Mnemonic C/20 EOC Access R/W Default Description The C/20 bit has priority over the other settings (C/10 EOC and IEND).
PAGE 29
Data Sheet Bit No. [2:0] Mnemonic VWEAK[2:0] ADP5065 Access R/W Default 011 = 3.0 V Description Weak battery voltage rising threshold. 000 = 2.7 V. 001 = 2.8 V. 010 = 2.9 V. 011 = 3.0 V. 100 = 3.1 V. 101 = 3.2 V. 110 = 3.3 V. 111 = 3.4 V. Table 21. Timer Settings, Register Address 0x06 Bit Descriptions Bit No.
PAGE 30
ADP5065 Bit No. 2 1 0 Data Sheet Mnemonic EN_BAT_INT EN_CHG_INT EN_VIN_INT Access R/W R/W R/W Default 0 0 0 Description When high, the battery voltage thresholds interrupt is allowed. When high, the charger mode change interrupt is allowed. When high, the VINx pin voltage thresholds interrupt is allowed. Table 25. Interrupt Active, Register Address 0x0A Bit Descriptions Bit No.
PAGE 31
Data Sheet ADP5065 Table 27. Charger Status Register 2, Register Address 0x0C Bit Descriptions Bit No. [7:5] Mnemonic THR_STATUS[2:0] Access R Default Not applicable 4 IPK_STAT R Not applicable 3 [2:0] Not Used BATTERY_STATUS[2:0] R R Not applicable Description THR pin status. 000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor OK. Peak current limit status bit.
PAGE 32
ADP5065 Data Sheet APPLICATIONS INFORMATION EXTERNAL COMPONENTS Inductor Selection The high switching frequency of the ADP5065 buck converter allows for the selection of small chip inductors. Suggested inductors are shown in Table 33. The peak-to-peak inductor current ripple is calculated using the following equation: VOUT × (VIN − VOUT ) VIN × f SW × L CEFF = COUT × (1 − TEMPCO) × (1 − TOL) where: CEFF is the effective capacitance at the operating voltage.
PAGE 33
Data Sheet ADP5065 VINx Capacitor Selection According to the USB 2.0 specification, USB peripherals have a detectable change in capacitance on VBUS when they are attached. The peripheral device VBUS bypass capacitance must be at least 1 µF but not larger than 10 µF. The combined capacitance for the VINx and CFILT pins must not exceed 10 µF at any temperature or dc bias condition. Suggestions for a VINx capacitor is given in Table 32.
PAGE 34
ADP5065 Data Sheet PCB LAYOUT GUIDELINES  Poor layout can affect ADP5065 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:   Place the inductor, input capacitor, and output capacitor close to the IC using short tracks.
PAGE 35
Data Sheet ADP5065 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5065 is a highly efficient USB compliant charger. However, if the device operates at high ambient temperatures and maximum current charging and loading conditions, the junction temperature can reach the maximum allowable operating limit (125°C). When the temperature exceeds 140°C, the ADP5065 turns off allowing the device to cool down.
PAGE 36
ADP5065 Data Sheet JUNCTION TEMPERATURE In cases where the ambient temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) (9) The typical θJA value for the 20-bump WLCSP is 46.8°C/W (see Table 5). A very important factor to consider is that θJA is based on a 4-layer, 4 in × 3 in, 2.
PAGE 37
Data Sheet ADP5065 FACTORY-PROGRAMMABLE OPTIONS Table 34. ADP5065 Fuse-Selectable Trim Options Parameter NTC Thermistor Type NTC Beta Value 10 kΩ 100 kΩ 3150 3350 3500 3650 3850 4000 4200 4400 ADP5065ACBZ-1-R7 Trim Setting 10 kΩ 3350 Rev.
PAGE 38
ADP5065 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 2.08 2.04 2.00 4 3 2 1 A BALL A1 IDENTIFIER B 2.75 2.71 2.67 2.00 REF C D E 0.50 REF BOTTOM VIEW TOP VIEW (BALL SIDE UP) (BALL SIDE DOWN) SEATING PLANE SIDE VIEW 1.50 REF COPLANARITY 0.04 0.360 0.320 0.280 0.270 0.240 0.210 10-30-2012-A 0.660 0.600 0.540 0.390 0.360 0.330 Figure 42.
PAGE 39
Data Sheet ADP5065 NOTES Rev.
PAGE 40
ADP5065 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09370-0-2/13(D) www.analog.com/ADP5065 Rev.