Datasheet

ADP5065 Data Sheet
Rev. D | Page 34 of 40
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5065 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
 Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
 Route the output voltage path away from both the inductor
and SWxnode to minimize noise and magnetic interference.
 Maximize the size of ground metal on the component side
to help with thermal dissipation.
 Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
E1D1
D4 E4C2
CFILT
SW1
SW2
ISO_S1
ISO_S2
ISO_B1
ISO_B2
VDDIO
PGND1 PGND2 AGND
IIN_EXT
TRK_EXT
V_WEAK_SET
THR
TO MCU
T
O MCU/N
C
T
O MCU/NC
R3/NC
(OPTIONAL)
+
ADP5065
C1 2.2µF
GRM21BR71E225K
C2 4.7µF
GRM219R61C475K
V
IN = 4.5V TO 5.5V
R5 NTC 10kΩ
(OPTIONAL)
R4
10kΩ
CONNECT
CLOSE TO
BATTERY
C4 22µF
GRM31CR61A226K
C3 22µF
GRM31CR61A226K
L1 1µH
LQH32PN1R0NN0
VIN1 VIN2
BAT_SNS
SYS_ON_OK
CONTROL
(INPUT CURRENT,
DC-DC)
CHARGE CONTROL
(CHARGE MODE,
BATTERY ISOLATION)
E2
SCL
SDA
VDDIO
TO MCU
TO MCU
R1
1.5kΩ
R2
1.5kΩ
A2
B1
A4
B2
A1
D3
E3
C3
C4
B3
B4
A3
D2
C1
09370-040
Figure 40. Reference Circuit Diagram
8mm
PGND
PGND
PGND
11.5mm
V
IN
ADP5065
C
IN
2.2µF
C
CFILT
4.7µF
C
ISO_S
22µF
L 1µH
C
ISO_B
22µF
0
9370-041
Figure 41. PCB Layout Suggestion