Datasheet

ManualsBrandsAnalog Devices ManualsADC - Analog to DigitalAnalog Front End IC 14bit LFCSP-

Photometric Front Ends

Data Sheet

ADPD1080/ADPD1081

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Multifunction photometric front end

Fully integrated AFE, ADC, LED drivers, and timing core

Enables ambient light rejection capability without the need

for photodiode optical filters

Three 370 mA LED peak current drivers

Flexible, multiple, short LED pulses per optical sample

20-bit burst accumulator enabling 20 bits per sample period

On-board sample to sample accumulator, enabling up to

27 bits per data read

Low power operation

SPI, I

C interface, and 1.8 V analog/digital core

Flexible sampling frequency ranging from 0.122 Hz to 2700 Hz

FIFO data operation

Qualified for automotive applications

APPLICATIONS

Wearable health and fitness monitors

Clinical measurements, for example, SpO

Industrial monitoring

Background light measurements

GENERAL DESCRIPTION

The ADPD1080/ADPD1081 are highly efficient, photometric

front ends, each with an integrated 14-bit analog-to-digital

converter (ADC) and a 20-bit burst accumulator that works

with flexible light emitting diode (LED) drivers. The ADPD1080/

ADPD1081 stimulate an LED and measures the corresponding

optical return signal. The data output and functional configuration

occur over a 1.8 V I

C interface on the ADPD1080 or a serial

port interface (SPI) on the ADPD1081. The control circuitry

includes flexible LED signaling and synchronous detection.

The analog front end (AFE) features rejection of signal offset and

corruption due to modulated interference commonly caused by

ambient light without the need for optical filters or dc cancellation

circuitry that requires external control.

Couple the ADPD1080/ADPD1081 with a low capacitance

photodiode of <100 pF for optimal performance. The ADPD1080/

ADPD1081 can be used with any LED. The ADPD1080 is available

in a 16-ball, 2.46 mm × 1.4 mm WLCSP and a 28-lead, 4 mm ×

4 mm LFCSP. The SPI only version, ADPD1081, is available in a

17-ball, 2.46 mm × 1.4 mm WLCSP.

Downloaded from Arrow.com.

Summary of content (74 pages)

PAGE 1
Photometric Front Ends ADPD1080/ADPD1081 Data Sheet FEATURES GENERAL DESCRIPTION Multifunction photometric front end Fully integrated AFE, ADC, LED drivers, and timing core Enables ambient light rejection capability without the need for photodiode optical filters Three 370 mA LED peak current drivers Flexible, multiple, short LED pulses per optical sample 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator, enabling up to 27 bits per data read Low power opera
PAGE 2
ADPD1080/ADPD1081 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LED Driver Pins and LED Supply Voltage.............................. 32 Applications ....................................................................................... 1 LED Driver Operation ............................................................... 32 General Description ......................................................................
PAGE 3
Data Sheet ADPD1080/ADPD1081 REVISION HISTORY 10/2018—Rev. A to Rev. B Changed TA = Full Operating Temperature Range to TA = 25°C ........................................................................ Throughout Changes to Features Section ............................................................ 1 Changes to ADPD1080WBCPZR7 Parameter, Table 1 ............... 6 Deleted Input Capacitance Parameter, Table 4.............................. 8 Changes to Digital Specifications Section.......................
PAGE 4
ADPD1080/ADPD1081 Data Sheet FUNCTIONAL BLOCK DIAGRAMS AVDD DVDD ADPD1080/ADPD1081 PDC PD1 1µF TIME SLOT A DATA AFE: SIGNAL CONDITIONING PD5 VREF WLCSP TIME SLOT SWITCH TIA BPF ±1 INTEGRATOR GPIO0 14-BIT ADC GPIO1 VBIAS AFE CONFIGURATION TIME SLOT B DATA A B TIME SLOT SELECT LEDX3 LEDX3 LEDX2 LEDX2 LED3 DRIVER LED3 LEVEL AND TIMING CONTROL LED2 DRIVER LED2 LEVEL AND TIMING CONTROL LED1 DRIVER LED1 LEVEL AND TIMING CONTROL DIGITAL DATAPATH AND INTERFACE CONTROL SDA SCL ADPD1081 O
PAGE 5
Data Sheet ADPD1080/ADPD1081 DVDD AVDD TIME SLOT SWITCH ANALOG BLOCK PDC AFE: SIGNAL CONDITIONING PD1 TIA PD5 BPF ADPD1080 LFCSP ±1 INTEGRATOR VBIAS VREF AFE: SIGNAL CONDITIONING PD2 TIA BPF PD6 14-BIT ADC VBIAS AFE: SIGNAL CONDITIONING PD3 TIA BPF PD7 ±1 INTEGRATOR AFE: SIGNAL CONDITIONING TIA PD8 AFE CONFIGURATION TIME SLOT B DATA SDA A SCL B VBIAS PD4 1µF TIME SLOT A DATA ±1 INTEGRATOR BPF TIME SLOT SELECT GPIO0 DIGITAL DATAPATH AND INTERFACE CONTROL GPIO1 ±1 INTEGRATOR
PAGE 6
ADPD1080/ADPD1081 Data Sheet SPECIFICATIONS TEMPERATURE AND POWER SPECIFICATIONS Operating Conditions Table 1. Parameter TEMPERATURE Operating Range ADPD1080WBCPZR7 Storage Range POWER SUPPLY VOLTAGE VDD Test Conditions/Comments Min Automotive grade only −40 −40 −65 Applied at the AVDD, DVDD, and VDD pins 1.7 Typ 1.8 Max Unit +85 +105 +150 °C °C °C 1.9 V Current Consumption AVDD = DVDD = 1.8 V, ambient temperature (TA) = 25°C, unless otherwise noted. Table 2.
PAGE 7
Data Sheet ADPD1080/ADPD1081 PERFORMANCE SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = 25°C, unless otherwise noted. Table 3.
PAGE 8
ADPD1080/ADPD1081 Data Sheet ANALOG SPECIFICATIONS AVDD = DVDD = 1.8 V, TA = 25°C, unless otherwise noted. Compensation of the AFE offset is explained in the AFE Operation section. Table 4.
PAGE 9
Data Sheet Parameter SYSTEM PERFORMANCE Total Output Noise Floor ADPD1080/ADPD1081 Test Conditions/Comments Normal mode; per pulse; per channel; no LED; photodiode capacitance (CPD) = 70 pF 25 kΩ; referred to ADC input 25 kΩ; referred to peak input signal for 2 µs LED pulse 25 kΩ; referred to peak input signal for 3 µs LED pulse 25 kΩ; saturation SNR per pulse per channel4 50 kΩ; referred to ADC input 50 kΩ; referred to peak input signal for 2 µs LED pulse 50 kΩ; referred to peak input signal for 3 µs LED
PAGE 10
ADPD1080/ADPD1081 Data Sheet DIGITAL SPECIFICATIONS DVDD = 1.7 V to 1.9 V, TA = -40°C to 105°C, unless otherwise noted. Table 5. Parameter LOGIC INPUTS (GPIOx, SCL1, SDA1, SCLK2, MOSI2, CS2) Input Voltage Level High Symbol Test Conditions/Comments Min VIH SCL1, SDA1 GPIOx, SCLK2, MOSI2, CS2 Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS Output Voltage Level High Low Output Voltage Level Low Output Current Level Low VIL 1 2 IIH IIL CIN VOH VOL VOL1 IOL Max Unit 0.7 × DVDD 0.
PAGE 11
Data Sheet ADPD1080/ADPD1081 TIMING SPECIFICATIONS DVDD = 1.7 V to 1.9 V, TA = −40°C to +105°C, unless otherwise noted. I2C Timing Specifications Table 6. Parameter I2C PORT SCL Frequency Minimum Pulse Width High Low Start Condition Hold Time Setup Time SDA Setup Time SCL and SDA Rise Time Fall Time Stop Condition Setup Time Symbol Test Conditions/Comments I2C port on ADPD1080 only.
PAGE 12
ADPD1080/ADPD1081 Data Sheet SPI Timing Specifications DVDD = 1.7 V to 1.9 V, TA = −40°C to +85°C, unless otherwise noted. Table 7.
PAGE 13
Data Sheet ADPD1080/ADPD1081 ABSOLUTE MAXIMUM RATINGS Table 8. ADPD1080 Absolute Maximum Rating RECOMMENDED SOLDERING PROFILE Parameter AVDD to AGND DVDD to AGND (LFCSP Only) GPIOx to AGND (LFCSP Only) DVDD to DGND (WLCSP Only) GPIOx to DGND (WLCSP Only) LEDXx to LGND SCL, SDA to DGND Junction Temperature Electrostatic Discharge (ESD) Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) Figure 5 and Table 11 provide details about the recommended soldering profile.
PAGE 14
ADPD1080/ADPD1081 Data Sheet 22 NIC 23 LEDX1 26 LGND 25 LEDX2 24 LEDX3 27 SCL 28 SDA PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 21 NIC GPIO0 1 GPIO1 2 AGND 4 VREF 5 AVDD 6 ADPD1080 TOP VIEW (Not to Scale) 20 NIC 19 NIC 18 NIC 17 NIC 16 NIC PD1 7 PD6 13 PD7 14 PDC 11 PD5 12 PD4 10 PD2 PD3 8 9 15 PD8 NOTES 1. NIC = NOT INTERNALLY CONNECTED (NONBONDED PAD). THIS PIN CAN BE GROUNDED. 2. EXPOSED PAD (DIGITAL GROUND). CONNECT THE EXPOSED PAD TO GROUND. 16110-006 DVDD 3 Figure 6.
PAGE 15
Data Sheet ADPD1080/ADPD1081 ADPD1080 A B C LEDX2 LGND LEDX3 LEDX1 SDA SCL GPIO0 DVDD DGND AGND D E GPIO1 VREF AVDD F PD5 PDC PD1 16110-007 TOP VIEW, BALL SIDE DOWN (Not to Scale) 1 2 3 Figure 7. 16-Ball WLCSP Pin Configuration (ADPD1080) Table 13. 16-Ball WLCSP Pin Function Descriptions (ADPD1080) Pin No.
PAGE 16
ADPD1080/ADPD1081 Data Sheet ADPD1081 LEDX2 LGND LEDX3 LEDX1 GPIO0 C GPIO1 MISO DGND D CS MOSI SCLK E VDD AGND VREF F PD5 PDC PD1 A B 16110-008 TOP VIEW, BALL SIDE DOWN (Not to Scale) 1 2 3 Figure 8. 17-Ball WLCSP Pin Configuration (ADPD1081) Table 14. 17-Ball WLCSP Pin Function Descriptions (ADPD1081) Pin No.
PAGE 17
Data Sheet ADPD1080/ADPD1081 TYPICAL PERFORMANCE CHARACTERISTICS 70 LED COARSE SETTING = 0xF 30 50 40 30 20 25 20 15 10 5 16110-009 10 0 32 33 34 35 36 37 38 FREQUENCY (Hz) 39 40 LED COARSE SETTING = 0x0 0 0 41 0.2 0.4 0.6 0.8 1.0 1.6 1.8 2.0 2.2 2.4 Figure 12. LED Driver Current vs. LED Driver Voltage at 10% Drive Strength, Fine Setting at Default 400 60 LED COARSE SETTING = 0xF 350 LED DRIVER CURRENT (mA) 50 40 30 20 10 300 250 200 150 100 16110-010 50 0 32.0 32.
PAGE 18
ADPD1080/ADPD1081 Data Sheet 45 0 AC PSRR (dB) –10 35 30 –20 –25 0 1 2 3 4 5 6 7 8 9 A B C D E –35 –40 F 1 LED FINE SETTING Figure 14. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0x0) 340 320 300 280 260 240 16110-016 220 200 0 1 2 3 4 5 6 7 8 9 A B C D E F LED FINE SETTING Figure 15. LED Driver Current vs. LED Fine Setting (Coarse Setting = 0xF) Rev. B | Page 18 of 74 Downloaded from Arrow.com.
PAGE 19
Data Sheet ADPD1080/ADPD1081 THEORY OF OPERATION INTRODUCTION DUAL TIME SLOT OPERATION The ADPD1080/ADPD1081 operate as a complete optical transceiver stimulating up to three LEDs and measuring the return signal on up to two separate current inputs. The core consists of a photometric front end coupled with an ADC, digital block, and three independent LED drivers.
PAGE 20
ADPD1080/ADPD1081 Data Sheet TIME SLOT SWITCH ADPD1080 LFCSP Input Configurations PD1 CH1 Up to eight photodiodes (PD1 to PD8) can be connected to the ADPD1080 for the LFCSP. The photodiode anodes are connected to the PD1 to PD8 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in seven different configurations depending on the settings of Register 0x14 (see Figure 18 through Figure 24).
PAGE 21
Data Sheet ADPD1080/ADPD1081 PD1 PD3 CH1 CH1 PD4 PD2 PD5 CH2 CH2 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 6 REGISTER 0x14[7:4] = 6 PD3 CH3 16110-023 PD6 Figure 23. PD3 to PD6 Connections with Register 0x14, Bits[11:8] and Bits[7:4] = 6 for the LFCSP PD5 PD4 CH1 CH4 PD6 PD7 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 7 REGISTER 0x14[7:4] = 7 Figure 22.
PAGE 22
ADPD1080/ADPD1081 Data Sheet WLCSP Input Configurations Up to two photodiodes can be connected to the PD1 and PD5 input pins of the ADPD1080 and ADPD1081 WLCSP models. The photodiode anodes are connected to the PD1 and PD5 input pins; the photodiode cathodes are connected to the cathode pin, PDC. The anodes are assigned in the configurations shown in Figure 25 and Figure 26 based on the bit settings of Register 0x14.
PAGE 23
Data Sheet ADPD1080/ADPD1081 ADJUSTABLE SAMPLING FREQUENCY Providing an External 32 kHz Clock Register 0x12 controls the sampling frequency setting of the ADPD1080/ADPD1081 and Register 0x4B, Bits[5:0] further tunes this clock for greater accuracy. An internal 32 kHz sample rate clock that also drives the transition of the internal state machine governs the sampling frequency. The maximum sampling frequencies for some sample conditions are listed in Table 3.
PAGE 24
ADPD1080/ADPD1081 Data Sheet STATE MACHINE OPERATION During each time slot, the ADPD1080/ADPD1081 operate according to a state machine. The state machine operates in the sequence shown in Figure 27. STANDBY REGISTER 0x10 = 0x0000 ULTRALOW POWER MODE NO DATA COLLECTION ALL REGISTER VALUES ARE RETAINED. this mode, the devices may consume higher current in program mode than in normal operation. To place the devices in program mode, write 0x1 to Register 0x10, Bits[1:0].
PAGE 25
Data Sheet ADPD1080/ADPD1081 LED Pulse and Sample can select from 2, 4, 8 … up to 128 samples to be averaged. Pulse data is still acquired by the AFE at the sampling frequency, fSAMPLE (Register 0x12), but new data is written to the registers at the rate of fSAMPLE/N every Nth sample. This new data consists of the sum of the previous N samples. The full 32-bit sum is stored in the 32-bit registers. However, before sending this data to the FIFO, a divide by N operation occurs.
PAGE 26
ADPD1080/ADPD1081 Data Sheet AFE OPERATION AFE INTEGRATION OFFSET ADJUSTMENT The timing within each pulse burst is important for optimizing the operation of the ADPD1080/ADPD1081. Figure 30 shows the timing waveforms for a single time slot as an LED pulse response propagates through the analog block of the AFE. The first graph, shown in green, shows the ideal LED pulsed output. The filtered LED response, shown in blue, shows the output of the analog integrator.
PAGE 27
Data Sheet ADPD1080/ADPD1081 LED_FALLING_EDGE = SLOTx_LED_OFFSET + SLOTx_LED_WIDTH and, AFE_INTEGRATION_FALLING_EDGE = 9 + SLOTx_AFE_OFFSET + SLOTx_AFE_WIDTH If both falling edges are set equal to each other, solve for SLOTx_AFE_OFFSET to obtain the following equation: AFE_OFFSET_STARTING_POINT = SLOTx_LED_ OFFSET + SLOTx_LED_WIDTH − 9 – SLOTx_AFE_ WIDTH Setting the AFE offset to any point in time earlier than the starting point is equivalent to setting the integration in the future; the AFE cannot integr
PAGE 28
ADPD1080/ADPD1081 Data Sheet I2C SERIAL INTERFACE 4. The ADPD1080 supports an I2C serial interface via the SDA (data) and SCL (clock) pins. All internal registers are accessed through the I2C interface. The ADPD1080 is an I2C only device and does not support an SPI. The ADPD1080 conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 05—9 October 2012, available from NXP Semiconductors. The I2C interface supports up to 1 Mbps data transfers.
PAGE 29
Data Sheet ADPD1080/ADPD1081 I2C WRITE REGISTER WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK DATA[15:8] ACK DATA[7:0] STOP ACK ACK I2C SINGLE WORD READ MODE REGISTER READ MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK ACK SLAVE ADDRESS + READ Sr ACK ACK DATA[15:8] ACK DATA[15:8] NACK STOP DATA[7:0] I2C MULTIWORD READ MODE REGISTER READ SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK Sr SLAVE ADDRESS + READ ACK ACK/NACK ACK DATA TRANSFER
PAGE 30
ADPD1080/ADPD1081 0 1 2 Data Sheet 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CS ADDRESS[6:0] MOSI DATA BYTE 1 DATA BYTE 2 16110-033 SCLK DATA BYTE N Figure 33. SPI Slave Write Clocking (Burst Write Mode, N Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS SCLK ADDRESS[6:0] MOSI DATA BYTE 1 MISO DATA BYTE 2 16110-034 W/R Figure 34.
PAGE 31
Data Sheet ADPD1080/ADPD1081 APPLICATIONS INFORMATION TYPICAL CONNECTION DIAGRAM 1.8V 0.1µF AVDD PD1 VLED 0.1µF AGND DGND LGND PD5 1.8V 10kΩ 4.7µF 10kΩ SCL LEDX1 VREF SDA TO DIGITAL INTERFACE GPIO0 GPIO1 1µF Figure 36. Typical Wrist-Based HRM Measurement 1 A Provide the 1.8 V supply, VDD, to AVDD and DVDD. The LED supply uses a standard regulator circuit according to the peak current requirements specified in Table 3 and calculated in the LED Driver Pins and LED Supply Voltage section.
PAGE 32
ADPD1080/ADPD1081 7 15 PD1 15 14 PD8 7 7 15 PD7 14 PD4 PDC PD5 PD6 PD2 PD1 PD8 15 8 PD8 14 16110-039 PD2 14 PD6 8 PD7 8 PDC 14 PD3 PD4 PD2 8 7 8 PD6 PD7 15 PDC PD5 7 14 PDC PD5 PDC PD1 PD1 15 PD3 7 8 PD3 PD4 PDC PD5 PD1 14 PDC 15 PD3 PD4 7 8 PD2 PD1 Data Sheet Figure 39. Photodiode Configuration Options for the ADPD1080 LFCSP Table 22.
PAGE 33
Data Sheet ADPD1080/ADPD1081 DETERMINING THE AVERAGE CURRENT The ADPD1080/ADPD1081 drive an LED in a series of short pulses. Figure 41 shows the typical ADPD1080/ADPD1081 configuration of an LED pulse burst sequence. 19µs 3µs ILED_MAX 4.0 3.5 3.0 2.5 2.0 1.5 16110-041 1.0 LED DRIVER CURRENT SETTING (mA) Figure 41. Typical LED Pulse Burst Sequence Configuration In this example, the LED pulse width, tLED_PULSE, is 3 µs, and the LED pulse period, tLED_PERIOD, is 19 µs.
PAGE 34
ADPD1080/ADPD1081 Data Sheet derating of the capacitor value over voltage, bias, temperature, and other factors over the life of the component. 4. LED INDUCTANCE CONSIDERATIONS The LED drivers (LEDXx) on the ADPD1080/ADPD1081 have configurable slew rate settings (Register 0x22, Bits[6:4], Register 0x23, Bits[6:4], and Register 0x24, Bits[6:4]). These slew rates are defined in Table 3. Even at the lowest setting, carefully consider board design and layout.
PAGE 35
Data Sheet ADPD1080/ADPD1081 Interrupt-Based Method Reading Data from Registers Using Interrupts To read data from the FIFO using an interrupt-based method, use the following procedure: The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Register 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B.
PAGE 36
ADPD1080/ADPD1081 Data Sheet Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. 2. CLOCKS AND TIMING CALIBRATION The ADPD1080/ADPD1081 operate using two internal time bases: a 32 kHz clock sets the sample timing, and a 32 MHz clock controls the timing of the internal functions, such as LED pulsing and data capture.
PAGE 37
Data Sheet ADPD1080/ADPD1081 Table 24. ADPD1080/ADPD1081 Settings Used for Timing Diagrams Shown in Figure 43 and Figure 44 Register 0x31 0x36 0x15 Setting 0x0118 0x0418 0x0120 SLEEP SLOT B SLOT A SLOT B 16110-043 SLOT A Description Time Slot A: 1 LED pulse Time Slot B: 4 LED pulses Time Slot A decimation = 4, Time Slot B decimation = 2 Figure 43.
PAGE 38
ADPD1080/ADPD1081 Data Sheet In such a case, the ADPD1080/ADPD1081 operate at 2× the sampling rate, and the LED settings can be reconfigured during the sleep period between samples. If identical LED settings (current and timing) are used for the LEDs being muxed, up to four LEDs can be sampled per sampling period without host intervention. An example of this configuration is shown in Figure 45.
PAGE 39
Data Sheet ADPD1080/ADPD1081 OPTIMIZING SNR PER WATT Tuning the Pulse Count The ADPD1080/ADPD1081 offer a variety of adjustable parameters to achieve the best signal. One of the key goals of system performance is to obtain the best system SNR for the lowest total power. This goal is often referred to as optimizing SNR per Watt. Even in systems where only the SNR matters and power is a secondary concern, there may be a lower power or a high power means of achieving the same SNR.
PAGE 40
ADPD1080/ADPD1081 Data Sheet Improving SNR Using Integrator Chopping pulses remain in the default polarity (noninverted). This configuration is achieved by setting Register 0x17, Bits[3:0] = 0xA and Register 0x1D, Bits[3:0] = 0xA for Time Slot A and Time Slot B, respectively. To complete the operation, the math must be adjusted using Register 0x58.
PAGE 41
Data Sheet Data Bit(s) [11:10] Bit Name FLT_MATH34_B [9:8] FLT_MATH34_A [6:5] FLT_MATH12_B [2:1] FLT_MATH12_A Description Time Slot B control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence). 00: add third and fourth. 01: add third and subtract fourth. 10: subtract third and add fourth. 11: subtract third and fourth.
PAGE 42
ADPD1080/ADPD1081 Data Sheet Table 26. Channel Power-Down Settings Channels Enabled Channel 1 Channel 2 Channel 1, Channel 2 Channel 3, Channel 4 Channel 2, Channel 3, Channel 4 All channels Register 0x3C, Bits[8:6] 0x7 0x0 0x0 0x0 0x0 0x0 OPTIMIZING DYNAMIC RANGE FOR HIGH AMBIENT LIGHT CONDITIONS Large amounts of ambient light use large amounts of the available dynamic range of the TIA.
PAGE 43
Data Sheet ADPD1080/ADPD1081 TIA ADC MODE Figure 49 shows a way to put the devices into a mode that effectively runs the TIA directly into the ADC without using the analog BPF and integrator. This mode is referred to as TIA ADC mode. There are two basic applications of TIA ADC mode. In normal operation, all background light is blocked from the signal chain and, therefore, cannot be measured. TIA ADC mode can measure the amount of background and ambient light.
PAGE 44
ADPD1080/ADPD1081 Data Sheet If this minimum value is above 0 LSB, the TIA is not saturated. However, take care, because even if the result is not 0 LSB, operating the device near saturation can quickly result in saturation if light conditions change. A safe operating region is typically at ¾ full scale and lower. Use Table 29 to determine how the input codes map to ADC levels on a per channel per pulse basis.
PAGE 45
Data Sheet ADPD1080/ADPD1081 Table 30. Configuration Registers to Switch Between the Normal Sample Mode and TIA ADC Mode Hex Addr.
PAGE 46
ADPD1080/ADPD1081 Data Sheet PULSE CONNECT MODE The ADPD1080 is configured to alternately measure the photodiode signal and the ECG signal from the AD8233 on consecutive time slots to provide fully synchronized PPG and ECG measurements. Data can be read out of the on-chip FIFO or straight from data registers. The ADPD1080 channel used to process the ECG signal is set up in TIA ADC mode, and the input bias voltage must be set to the 0.
PAGE 47
Data Sheet ADPD1080/ADPD1081 FLOAT MODE Float Mode Measurement Cycle The ADPD1080/ADPD1081 has a unique operating mode, float mode, that allows excellent SNR at low power in low light situations. In float mode, the photodiode is first preconditioned to a known state and then the photodiode anode is disconnected from the receive path of the ADPD1080/ ADPD1081 for a preset amount of float time.
PAGE 48
ADPD1080/ADPD1081 Data Sheet 25µs 30µs 35µs A D E CONNECT/FLOAT B C +PHASE F –PHASE INTEGRATOR CHARGE ON PD TIA OUTPUT DON’T CARE INTEGRATOR RESPONSE 16110-050 INTEGRATOR RESET ADC READ Figure 52. Float Mode Measurement Cycle Timing Diagram Float Mode Limitations PD BEGINS TO FORWARD BIAS RECOMMENDED FLOAT MODE OPERATING REGION FLOAT TIME (µs) 16110-051 INTEGRATED CHARGE ON PD (pC) When using float mode, the limitations of the mode must be well understood.
PAGE 49
Data Sheet ADPD1080/ADPD1081 than the second pulse. After the two measurements are taken, Measurement 1 is subtracted from Measurement 2, which effectively cancels out any offset and drift common to both measurements. What is left is an ambient light measurement based on an amount of charge that is integrated over a time that is the difference of the first and second float times.
PAGE 50
ADPD1080/ADPD1081 Group Float Mode Timing Data Sheet Register Name FLT_PRECON_x Register Time Slot A Time Slot B 0x5E, Bits[12:8] 0x59, Bits[12:8] SLOTx_PERIOD SLOTx_PERIOD SLOTx_LED_WIDTH 0x31, Bits[7:0] 0x37, Bits[1:0] 0x30, Bits[12:8] 0x36, Bits[7:0] 0x37, Bits[9:8] 0x35, Bits[12:8] SLOTx_LED_OFFSET 0x30, Bits[7:0] 0x35, Bits[7:0] SLOTx_AFE_WIDTH SLOTx_AFE_OFFSET 0x39, Bits[15:11] 0x39, Bits[10:0] 0x3B, Bits[15:11] 0x3B, Bits[10:0] SLOTx_PULSES 0x31, Bits[15:8] 0x36, Bits[15:8] Float Mode
PAGE 51
Data Sheet ADPD1080/ADPD1081 Table 32.
PAGE 52
ADPD1080/ADPD1081 Data Sheet the photodiode causes the integrator to increase with the negative going output signal from the TIA. pulses while subtracting the first and fourth pulses, effectively cancelling out the ambient light and electrical offsets and drift. The LED flashes in the second and third pulses of the four pulse sequence. Setting Register 0x58, Bits[6:5] = 2 and Register 0x58, Bits[11:10] = 1 forces the device to add the second and third A comparison of float ambient mode vs.
PAGE 53
Data Sheet ADPD1080/ADPD1081 Monitoring Ambient Light Levels in Float LED Mode In real-world applications, it is common for the ambient light levels to change constantly. When using float LED mode, increasing the amount of ambient light can approach levels where the ambient light uses an unacceptable amount of dynamic range of the charge that can be stored on the photodiode capacitance.
PAGE 54
ADPD1080/ADPD1081 Data Sheet REGISTER LISTING The recommended values are not shown. Only power-on reset values are shown in Table 36. The recommended values are largely dependent on use case. Table 36. Numeric Register Listing Hex. Addr.
PAGE 55
Data Sheet ADPD1080/ADPD1081 Hex. Addr.
PAGE 56
ADPD1080/ADPD1081 Data Sheet Hex. Addr.
PAGE 57
Data Sheet Hex. Addr.
PAGE 58
ADPD1080/ADPD1081 Data Sheet LED CONTROL REGISTERS Table 37.
PAGE 59
Data Sheet Address 0x24 0x25 0x30 ADPD1080/ADPD1081 Data Bit [6:4] Default Value 0x0 Access R/W Name ILED1_SLEW [3:0] 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0] 0x0 R/W ILED2_COARSE [15:11] 0xC R/W ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE [15:13] [12:8] [7:0] 0x0 0x3 0x20 R/W R/W R/W Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET Des
PAGE 60
ADPD1080/ADPD1081 Data Sheet Address 0x31 Data Bit [15:8] Default Value 0x08 Access R/W Name SLOTA_PULSES 0x34 [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] [7:0] 0x00 0x0 0x3 0x20 0x08 0x18 R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_PULSES SLOTB_PERIOD 0x35 0x36 R/W R/W Description LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A.
PAGE 61
Data Sheet Address 0x54 0x55 ADPD1080/ADPD1081 Data Bit [15:14] [13:12] Default Value 0x0 0x0 Access R/W R/W Name Reserved SLEEP_V_CATHODE [11:10] 0x0 R/W SLOTB_V_CATHODE [9:8] 0x0 R/W SLOTA_V_CATHODE 7 0x0 R/W REG54_VCAT_ENABLE [6:0] [15:12] [11:10] 0x20 0x0 0x0 R/W R/W R/W Reserved Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 [7:6] 0x0 R/W SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 Rev. B | Page 61 of 74 Downloaded from Arrow.com.
PAGE 62
ADPD1080/ADPD1081 Address Data Sheet Data Bit [3:2] Default Value 0x0 Access R/W Name SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 Description TIA gain for Time Slot A, Channel 3 when Register 0x42, Bit 6 = 1. 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. TIA gain for Time Slot A, Channel 2 when Register 0x42, Bit 6 = 1. 0: 200 kΩ 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. Table 39.
PAGE 63
Data Sheet ADPD1080/ADPD1081 Address Data Bit [1:0] Default Value 0x0 Access R/W Name SLOTA_TIA_GAIN 0x43 [15:0] 0xADA5 R/W SLOTA_AFE_CFG Description Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When this bit is disabled, it is for all four Time Slot A channel, TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. AFE connection in Time Slot A. 0xADA5: analog full path mode (TIA_BPF_INT_ADC).
PAGE 64
ADPD1080/ADPD1081 Data Sheet Address Data Bit [1:0] Default Value 0x0 Access R/W Name SLOTB_TIA_GAIN 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CFG Description Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_ IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 kΩ. 1: 100 kΩ. 2: 50 kΩ. 3: 25 kΩ. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIA_BPF_INT_ADC).
PAGE 65
Data Sheet ADPD1080/ADPD1081 Address Data Bit [13:0] Default Value 0x0 Access R/W Name BG_THRESH_B 0x3E [15:14] 0x0 R/W FLT_LED_SELECT_A 0x3F 13 [12:8] [7:0] [15:14] 0 0x03 0x20 0x0 R/W R/W R/W R/W Reserved FLT_LED_WIDTH_A FLT_LED_OFFSET_A FLT_LED_SELECT_B 13 [12:8] [7:0] [15:12] [11:10] 0 0x03 0x20 0x0 0x0 R/W R/W R/W R/W R/W Reserved FLT_LED_WIDTH_B FLT_LED_OFFSET_B Reserved FLT_MATH34_B [9:8] 0x0 R/W FLT_MATH34_A 7 0x0 R/W ENA_INT_AS_BUF [6:5] 0x0 R/W FLT_MATH12_B [4:3] [
PAGE 66
ADPD1080/ADPD1081 Address 0x59 0x5A 0x5E Data Sheet Data Bit 15 [14:13] Default Value 0x0 0x0 Access R/W R/W Name Reserved FLT_EN_B [12:8] 0x08 R/W FLT_PRECON_B [7:0] [15:12] 0x08 0x0 R/W R/W Reserved FLT_LED_FIRE_B [11:8] 0x0 R/W FLT_LED_FIRE_A [7:0] 15 [14:13] 0x10 0x0 0x0 R/W R/W R/W Reserved Reserved FLT_EN_A [12:8] 0x08 R/W FLT_PRECON_A [7:0] 0x08 R/W Reserved Description Write 0x0. 0: default setting, float disabled for Time Slot B. 1: reserved. 2: reserved.
PAGE 67
Data Sheet Address 0x02 0x06 0x08 0x09 0x0A 0x0B ADPD1080/ADPD1081 Data Bit 7 6 Default Value 0x1 0x1 Access R/W R/W Name Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:10] 9 0x1F 0x00 0x0 R/W R/W R/W Reserved Reserved GPIO1_DRV 8 0x0 R/W GPIO1_POL [7:3] 2 0x00 0x0 R/W R/W Reserved GPIO0_ENA 1 0x0 R/W GPIO0_DRV 0 0x0 R/W GPIO0_POL [15:14] [13:8] 0x0 0x00 R/W R/W Reserved FIFO_THRESH [7:0] [15:8] [7:0] [15:8] [7:1] 0 [15:12] [11:0] 0x00 0x0A 0x16 0x00 0x64
PAGE 68
ADPD1080/ADPD1081 Data Sheet Data Bit Default Value Access Name [7:5] [4:0] 0x0 0x00 R/W R/W Reserved GPIO0_ALT_CFG 0x0D [15:0] 0x0000 R/W SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x0000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT Address Description 0x05: Time Slot A pulse output. 0x06: Time Slot B pulse output. 0x07: pulse output of both time slots.
PAGE 69
Data Sheet Address 0x38 0x4B 0x4D ADPD1080/ADPD1081 Data Bit [11:9] [8:6] Default Value 0x0 0x0 Access R/W R/W Name Reserved SLOTB_FIFO_MODE 5 [4:2] 0x0 0x0 R/W R/W SLOTB_EN SLOTA_FIFO_MODE 1 0 [15:0] [15:9] 8 0x0 0x0 0x0000 0x13 0x0 R/W R/W R/W R/W R/W Reserved SLOTA_EN EXT_SYNC_STARTUP Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 [5:0] 0x0 0x12 R/W R/W Reserved CLK32K_ADJUST [15:8] [7:0] 0x00 0x98 R/W R/W Reserved CLK32M_ADJUST Description Reserved. Time Slot B FIFO data format.
PAGE 70
ADPD1080/ADPD1081 Address 0x4F 0x50 0x5F Data Sheet Data Bit [15:8] 7 6 5 4 [3:2] Default Value 0x20 0x1 0x0 0x0 0x1 0x0 Access R/W R/W R/W R/W R/W R/W Name Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W GPIO0_IE Reserved Reserved GPIO1_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] [15:3] 2 0x00 0x0000 0x0 R/W R/W R/W Reserved Reserved SLOTB_DATA_HOLD 1 0x0 R/W SLOTA_DATA_HOLD 0 0x0 R/W DIGITAL_CLOCK_ENA Description Write 0x20.
PAGE 71
Data Sheet ADPD1080/ADPD1081 ADC REGISTERS Table 43.
PAGE 72
ADPD1080/ADPD1081 Data Sheet DATA REGISTERS Table 44.
PAGE 73
Data Sheet ADPD1080/ADPD1081 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.25 0.20 0.15 4.10 4.00 SQ 3.90 PIN 1 INDICATOR AREA 0.40 BSC P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 28 22 1 21 2.70 2.60 SQ 2.50 EXPOSED PAD 15 0.45 0.40 0.35 0.80 0.75 0.70 SIDE VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-003523 SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 74
ADPD1080/ADPD1081 Data Sheet 1.44 1.40 1.36 3 2 1 A BALL A1 IDENTIFIER B 2.00 REF 2.50 2.46 2.42 C D 0.40 BSC E F BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.80 REF 0.330 0.300 0.270 END VIEW COPLANARITY 0.05 SEATING PLANE PKG-005139 0.300 0.260 0.220 0.230 0.200 0.170 03-03-2016-A 0.560 0.500 0.440 TOP VIEW Figure 58.