Datasheet

Data Sheet ADPD1080/ADPD1081
Rev. B | Page 67 of 74
Address Data Bit
Default
Value Access Name Description
7 0x1 R/W Reserved Write 0x1.
6 0x1 R/W SLOTB_INT_MASK Sends an interrupt on the Time Slot B sample. Write a 1 to disable
the interrupt. Write a 0 to enable the interrupt.
5 0x1 R/W SLOTA_INT_MASK Sends an interrupt on the Time Slot A sample. Write a 1 to disable
the interrupt. Write a 0 to enable the interrupt.
[4:0] 0x1F R/W Reserved Write 0x1F.
0x02 [15:10] 0x00 R/W Reserved Write 0x0000.
9 0x0 R/W GPIO1_DRV GPIO1 drive.
0: the GPIO1 pin is always driven.
1: the GPIO1 pin is driven when the interrupt is asserted; otherwise,
it is left floating and requires a pull-up or pull-down resistor,
depending on polarity (operates as open drain). Use this setting if
multiple devices must share the GPIO1 pin.
8 0x0 R/W GPIO1_POL GPIO1 polarity.
0: the GPIO1 pin is active high.
1: the GPIO1 pin is active low.
[7:3] 0x00 R/W Reserved Write 0x00.
2 0x0 R/W GPIO0_ENA GPIO0 pin enable.
0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of interrupt
status. The status register (Address 0x00) remains active.
1: enable the GPIO0 pin.
1 0x0 R/W GPIO0_DRV GPIO0 drive.
0: the GPIO0 pin is always driven.
1: the GPIO0 pin is driven when the interrupt is asserted; otherwise,
it is left floating and requires a pull-up or pull-down resistor,
depending on polarity (operates as open drain). Use this setting if
multiple devices must share the GPIO0 pin.
0 0x0 R/W GPIO0_POL GPIO0 polarity.
0: the GPIO0 pin is active high.
1: the GPIO0 pin is active low.
0x06 [15:14] 0x0 R/W Reserved Write 0x0.
[13:8] 0x00 R/W FIFO_THRESH FIFO length threshold. An interrupt is generated when the number
of data-words in the FIFO exceeds the value in FIFO_THRESH. The
interrupt pin automatically deasserts when the number of data-
words available in the FIFO no longer exceeds the value in
FIFO_THRESH.
[7:0] 0x00 R/W Reserved Write 0x00.
0x08 [15:8] 0x0A R REV_NUM Revision number.
[7:0] 0x16 R DEV_ID Device ID.
0x09 [15:8] 0x00 W ADDRESS_WRITE_KEY Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access.
[7:1] 0x64 R/W SLAVE_ADDRESS I
2
C slave address.
0 0x0 R Reserved Do not access.
0x0A [15:12] 0x0 R Reserved Write 0x0.
[11:0] 0x000 R CLK_RATIO When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the
device calculates the number of 32 MHz clock cycles in two cycles of
the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in
the CLK_RATIO bits.
0x0B [15:13] 0x0 R/W Reserved Write 0x0.
[12:8] 0x00 R/W GPIO1_ALT_CFG Alternate configuration for the GPIO1 pin.
0x00: GPIO1 is backward compatible to the ADPD103 PDSO pin
functionality.
0x01: interrupt function provided on GPIO1, as defined in Register 0x01.
0x02: asserts at the start of the first time slot, deasserts at end of last
time slot.
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