2/40-Bit IEEE Floating-Point DSP Microprocessor Specification Sheet

ADSP-21020
REV. C
–18–
Memory Read
K/B/T Grade K/B/T Grade B/T Grade K Grade
20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence*
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Timing Requirement:
t
DAD
Address, Select to Data Valid 37 27 20 17 37 + DT ns
t
DRLD
xRD Low to Data Valid 24 18 13 11 24 + 5DT/8 ns
t
HDA
Data Hold from Address, Select 0 0 0 0 ns
t
HDRH
Data Hold from xRD High –1 –1 –1 –1 ns
t
DAAK
xACK Delay from Address 27 18 12 9 27 + 7DT/8 ns
t
DRAK
xACK Delay from xRD Low 15 10 6 5 15 + DT/2 ns
t
SAK
xACK Setup before CLKIN High 14 12 10 9 14 + DT/4 ns
t
HAK
xACK Hold after CLKIN High 0 0 0 0 ns
Switching Characteristic:
t
DARL
Address, Select to xRD Low 8 4 2 0 8 + 3DT/8 ns
t
DAP
xPAGE Delay from Address, Select 1 1 1 1 ns
t
DCKRL
CLKIN High to xRD Low 16 26 13 24 12 22 11 21 16 + DT/4 26 + DT/4 ns
t
RW
xRD Pulse Width 26 20 15 13 26 + 5DT/8 ns
t
RWR
xRD High to xRD, xWD Low 17 13 11 9 17 + 3DT/8 ns
NOTES
*DT = t
CK
– 50 ns
x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.