Datasheet

Rev. D | Page 14 of 52 | May 2013
ADSP-21061/ADSP-21061L
ADSP-21061 SPECIFICATIONS
OPERATING CONDITIONS (5 V)
ELECTRICAL CHARACTERISTICS (5 V)
K Grade
Parameter Description Min Nom Max Unit
V
DD
Supply Voltage 4.75 5.0 5.25 V
T
CASE
Case Operating Temperature 0 85 C
V
IH
1
1
1
Applies to input and bidirectional pins: DATA
47–0
, ADDR
31–0
, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR
6–1
, ID
2–0
, RPBA, CPA, TFS0,
TFS1, RFS0, RFS1, EBOOT, BMS
, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
High Level Input Voltage @ V
DD
= Max 2.0 V
DD
+ 0.5 V
V
IH
2
2
2
Applies to input pins: CLKIN, RESET, TRST.
High Level Input Voltage @ V
DD
= Max 2.2 V
DD
+ 0.5 V
V
IL
1, 2
Low Level Input Voltage @ V
DD
= Min –0.5 +0.8 V
Parameter Description Test Conditions Min Max Unit
V
OH
1, 2
High Level Output Voltage @ V
DD
= Min, I
OH
= –2.0 mA 4.1 V
V
OL
1, 2
Low Level Output Voltage @ V
DD
= Min, I
OL
= 4.0 mA 0.4 V
I
IH
3, 4
High Level Input Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
IL
3
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
ILP
4
Low Level Input Current @ V
DD
= Max, V
IN
= 0 V 150 μA
I
OZH
5, 6, 7, 8
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 10 μA
I
OZL
5
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 10 μA
I
OZHP
Three-State Leakage Current @ V
DD
= Max, V
IN
= V
DD
Max 350 μA
I
OZLC
7
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 1.5 mA
I
OZLA
9
Three-State Leakage Current @ V
DD
= Max, V
IN
= 1.5 V 350 μA
I
OZLAR
8
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 4.2 mA
I
OZLS
6
Three-State Leakage Current @ V
DD
= Max, V
IN
= 0 V 150 μA
C
IN
10, 11
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 2.5 V 4.7 pF
1
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
, 3-0, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,
BR
6–1
, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.
2
See “Output Drive Currents” on Page 44 for typical drive current capabilities.
3
Applies to input pins: ACK, SBTS, IRQ
2–0
, HBR, CS, DMAR1, DMAR2, ID
2–0
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.
4
Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI, EMU.
5
Applies to three-statable pins: DATA
47–0
, ADDR
31–0
, MS
3–0
, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3–0
, HBG, REDY, DMAG1, DMAG2, BMS, BR
6–1
, TFSx, RFSx,
TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061 is not requesting bus
mastership.)
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
7
Applies to CPA pin.
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID
2–0
= 001 and another ADSP-21061L
is not requesting bus mastership).
9
Applies to ACK pin when keeper latch enabled.
10
Applies to all signal pins.
11
Guaranteed but not tested.