Datasheet

Rev. D | Page 24 of 52 | May 2013
ADSP-21061/ADSP-21061L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD
, WR, and
DMAGx
strobe timing parameters only applies to asynchronous
access mode.
Table 12. Memory Read—Bus Master
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2
18 + DT+W ns
t
DRLD
RD Low to Data Valid
1
12 + 5DT/8 + W ns
t
HDA
Data Hold from Address, Selects
3
0.5 ns
t
HDRH
Data Hold from RD High
3
2.0 ns
t
DAAK
ACK Delay from Address, Selects
2, 4
15 + 7DT/8 + W ns
t
DSAK
ACK Delay from RD Low
4
8 + DT/2 + W ns
Switching Characteristics
t
DRHA
Address, Selects Hold After RD High 0+H ns
t
DARL
Address, Selects to RD Low
2
2 + 3DT/8 ns
t
RW
RD Pulse Width 12.5 + 5DT/8 + W ns
t
RWR
RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI ns
t
SADADC
Address, Selects Setup Before ADRCLK High
2
0 + DT/4 ns
W = (number of wait states specified in WAIT register) ⴛ t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Data delay/setup: user must meet t
DAD
or t
DRLD
or synchronous spec t
SSDATI
.
2
The falling edge of MSx, SW, BMS is referenced.
3
Data hold: user must meet t
HDA
or t
HDRH
or synchronous spec t
HSDATI
. See Example System Hold Time Calculation on Page 43 for the calculation of hold times given capacitive
and dc loads.
4
ACK delay/setup: user must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
(Table 13 on Page 25) for deassertion of ACK (Low), all three specifications must be met
for assertion of ACK (High).
Figure 14. Memory Read—Bus Master
WR, DMAG
ACK
DATA
RD
ADDRESS
MSX, SW
BMS
t
DARL
t
RW
t
DAD
t
SADADC
t
DAAK
t
HDRH
t
HDA
t
RWR
t
DRLD
ADDRCLK
(OUT)
t
DRHA
t
DSAK