Datasheet

Rev. D | Page 40 of 52 | May 2013
ADSP-21061/ADSP-21061L
Figure 24. Serial Ports
DT
DT
DRIVE EDGE DRIVE EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK
(INT)
TCLK/RCLK
TCLK
(EXT)
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
DATA RECEIVE— INTERNAL CLOCK
DATA RECEIVE— EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
DATA TRANSMIT— INTERNAL CLOCK
DATA TRANSMIT— EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTTE
t
DDTEN
t
DDTTI
t
DDTIN
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSE
t
HOFSE
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
t
DDTI
t
HDTI
t
SFSI
t
HFSI
t
SCLKIW
t
DFSI
t
HOFSI
t
DDTE
t
HDTE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
CLKIN
t
DPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
TCLK, RCLK
TFS,RFS,DT
TCLK (INT)
RCLK (INT)
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
t
DCLK
LOW TO HIGH ONLY
t
STFSCK
CLKIN
t
HTFSCK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS,AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESHMULTIPROCESSING.
TFS (EXT)