Datasheet

ADSP-21061/ADSP-21061L
Rev. D | Page 43 of 52 | May 2013
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
L
, and the
load current, I
L
. This decay time can be approximated by the
following equation:
The output disable time t
DIS
is the difference between
t
MEASURED
and t
DECAY
as shown in Figure 27. The time t
MEASURED
is
the interval from when the reference signal switches to when the
output voltage decays V from the measured output high or
output low voltage. t
DECAY
is calculated with test loads C
L
and I
L
,
and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose V
to be the difference between the ADSP-21061’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. C
L
is the total bus capacitance (per data
line), and I
L
is the total leakage or three-state current (per data
line). The hold time will be t
DECAY
plus the minimum disable
time (i.e., t
DATRWH
for the write cycle).
Output Drive Characteristics
Figure 30 through Figure 37 show typical characteristics for the
output drivers of the ADSP-21061 (5 V) and ADSP-21061L
(3 V). The curves represent the current drive capability and
switching behavior of the output drivers as a function of
resistive and capacitive loading.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 31,
Figure 32, Figure 35, and Figure 36 show how output rise time
varies with capacitance. Figure 33 and Figure 37 show graphi-
cally how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output dis-
able delays; see the previous section Output Disable Time under
Test Conditions.) The graphs of Figure 31, Figure 32, Figure 35,
and Figure 36 may not be linear outside the ranges shown.
Figure 27. Output Enable/Disable
P
EXT
C
L
V
I
L
---------------
=
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
- ⌬V
V
OL (MEASURED)
+ ⌬V
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH IMPEDANCE STATE.
TESTCONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V.
OUTPUT STOPS
DRIVING
t
ENA
t
DECAY
Figure 28. Equivalent Device Loading for AC Measurements (Includes All
Fixtures)
Figure 29. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
INPUT
OR
OUTPUT
1.5V 1.5V