Datasheet

ADSP-21061/ADSP-21061L
Rev. D | Page 5 of 52 | May 2013
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
DMA transfers between external memory and external periph-
eral devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.
Figure 3. Shared Memory Multiprocessing System
ADDR31–0
CPA
BMS
C
O
N
T
R
O
L
ADSP-21061 #1
5
CONTROL
ADSP-21061 #2
ADDR31–0
CONTROL
ADSP-21061 #3
5
ID2–0
RESET
RPBA
CLKIN
ID2–0
RESET
RPBA
ID2–0
RESET
RPBA
CLKIN
ADSP-21061 #6
ADSP-21061 #5
ADSP-21061 #4
CLOCK
RESET
ADDR
DATA
HOSTPROCESSOR
INTERFACE (OPTIONAL)
ACK
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT EPROM (OPTIONAL)
RDx
MS3–0
SBTS
CS
ACK
ADDR31–0
CLKIN
3
001
PAGE
3
010
3
011
BR1
BR2–6
REDY
HBG
HBR
CS
WE
WRx
5
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
DATA47–0
BR1–2, BR4–6
BR3
DATA47–0
BR1, BR3–6
BR2
DATA47–0
BUS
PRIORITY
CPA