Datasheet

ADSP-21061/ADSP-21061L
Rev. D | Page 25 of 52 | May 2013
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD
, WR, and
DMAGx
strobe timing parameters only applies to asynchronous
access mode.
Table 13. Memory Write—Bus Master
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
15 + 7DT/8 + W ns
t
DSAK
ACK Delay from WR Low
1
8 + DT/2 + W ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
17 + 15DT/16 + W ns
t
DAWL
Address, Selects to WR Low
2
3 + 3DT/8 ns
t
WW
WR Pulse Width 13 + 9DT/16 + W ns
t
DDWH
Data Setup Before WR High 7 + DT/2 + W ns
t
DWHA
Address Hold After WR Deasserted 1 + DT/16 + H ns
t
DATRWH
Data Disable After WR Deasserted
3
1 + DT/16 +H 6 + DT/16+H ns
t
WWR
WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H ns
t
DDWR
Data Disable Before WR or RD Low 5 + 3DT/8 + I ns
t
WDE
WR Low to Data Enabled –1 + DT/16 ns
t
SADADC
Address, Selects to ADRCLK High
2
0 + DT/4 ns
W = (number of wait states specified in WAIT register) × t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
ACK delay/setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SAKC
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(high).
2
The falling edge of MSx, SW, BMS is referenced.
3
For more information, see Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
Figure 15. Memory Write—Bus Master
RD, DMAG
ACK
DATA
WR
ADDRESS
MSX, SW
BMS
t
WW
t
SADADC
t
DAAK
t
WWR
ADRCLK
(OUT)
t
DWHA
t
DSAK
t
DAWL
t
WDE
t
DDWR
t
DATRWH
t
DDWH
t
DAWH