Datasheet

Rev. D | Page 42 of 52 | May 2013
ADSP-21061/ADSP-21061L
JTAG Test Access Port and Emulation
For JTAG Test Access Port and Emulation, see Table 28 and
Figure 26.
Table 28. JTAG Test Access Port and Emulation
Parameter
5 V and 3.3 V
Unit
Min Max
Timing Requirements
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High t
CK
ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
System Inputs Setup Before TCK Low
1
7ns
t
HSYS
System Inputs Hold After TCK Low
1
18 ns
t
TRSTW
TRST Pulse Width 4t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 13 ns
t
DSYS
System Outputs Delay After TCK Low
2
18.5 ns
1
System Inputs = DATA47–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, CPA, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
2
System Outputs = DATA47–0, ADDR31–0, MS3–0, RD, WR, SW, ACK, ADRCLK, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, FLAG3–0, TIMEXP, DT0, DT1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
Figure 26. JTAG Test Access Port and Emulation
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS