Datasheet

Rev. F | Page 20 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
EXTERNAL POWER DISSIPATION (3.3 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
P
INT
= I
DDIN
u V
DD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• the number of output pins that switch during each cycle
(O)
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
• their voltage swing (V
DD
)
and is calculated by:
P
EXT
= O u C u V
DD
2
u f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t
CK
). The write
strobe can switch every cycle at a frequency of 1/t
CK
. Select pins
switch at 1/(2t
CK
), but selects can switch on each cycle.
Example: Estimate P
EXT
with the following assumptions:
• A system with one bank of external data memory RAM
(32-bit)
• Four 128K u 8 RAM chips are used, each with a load of
10 pF
• External data memory writes occur every other cycle, a rate
of 1/(4t
CK
), with 50% of the pins switching
• The instruction cycle rate is 40 MHz (t
CK
= 25 ns)
The P
EXT
equation is calculated for each class of pins that can
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
TOTAL
= P
EXT
+ (I
DDIN 2
u 5.0 V)
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed Table 7 may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table 6. External Power Calculations (3.3 V Devices)
Pin Type No. of Pins % Switching u C u f u V
DD
2
= P
EXT
Address 15 50 u 44.7 pF u 10 MHz u 10.9 V = 0.037 W
MS0
10 u 44.7 pF u 10 MHz u 10.9 V = 0.000 W
WR
1– u 44.7 pF u 20 MHz u 10.9 V = 0.010 W
Data 32 50 u 14.7 pF u 10 MHz u 10.9 V = 0.026 W
ADDRCLK 1 – u 4.7 pF u 20 MHz u 10.9 V = 0.001 W
P
EXT
= 0.074 W
Table 7. Absolute Maximum Ratings
Parameter
ADSP-21060/ADSP-21060C
ADSP-21062
ADSP-21060L/ADSP-21060LC
ADSP-21062L
5 V 3.3 V
Supply Voltage (V
DD
) –0.3 V to +7.0 V –0.3 V to +4.6 V
Input Voltage –0.5 V to V
DD
+ 0.5 V –0.5 V to V
DD
+0.5 V
Output Voltage Swing –0.5 V to V
DD
+ 0.5 V –0.5 V to V
DD
+ 0.5 V
Load Capacitance 200 pF 200 pF
Storage Temperature Range –65qC to +150qC–65qC to +150qC
Lead Temperature (5 seconds) 280qC280qC
Junction Temperature Under Bias 130qC130qC