Datasheet

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F | Page 29 of 64 | March 2008
Synchronous Read/Write—Bus Slave
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
The bus master must meet the bus slave timing requirements.
Table 17. Synchronous Read/Write—Bus Slave
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SADRI
Address, SW Setup Before CLKIN 15 + DT/2 ns
t
HADRI
Address, SW Hold After CLKIN 5 + DT/2 ns
t
SRWLI
RD/WR Low Setup Before CLKIN
1
9.5 + 5DT/16 ns
t
HRWLI
RD/WR Low Hold After CLKIN
2
–4 – 5DT/16 8 + 7DT/16 ns
t
RWHPI
RD/WR Pulse High 3 ns
t
SDATWH
Data Setup Before WR High 5 ns
t
HDATWH
Data Hold After WR High 1 ns
Switching Characteristics
t
SDDATO
Data Delay After CLKIN
3
18 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
4
0 – DT/8 7 – DT/8 ns
t
DACKAD
ACK Delay After Address, SW
5
9ns
t
ACKTR
ACK Disable After CLKIN
5
–1 – DT/8 6 – DT/8 ns
1
t
SRWLI
(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min)= 4 + DT/8.
2
For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max.
3
For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max.
4
See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
5
t
DACKAD
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times
greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state
of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACKTR
.
Figure 17. Synchronous Read/Write—Bus Slave
CLKIN
ADDRESS
ACK
RD
DATA
(OU T)
WR
WRITE ACCESS
DATA
(IN)
READ ACCESS
t
SADRI
t
HADRI
t
DACKAD
t
ACKTR
t
HRWLI
t
SRWLI
t
SDDATO
t
DATTR
t
SRW LI
t
HRWLI
t
HDATWH
t
SDATWH
t
RWHPI
t
RWHPI