Datasheet

Rev. F | Page 34 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Three-State Timing—Bus Master/ Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS
pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS
pin.
Table 21. Three-State Timing—Bus Master, Bus Slave
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
STSCK
SBTS Setup Before CLKIN 12 + DT/2 ns
t
HTSCK
SBTS Hold Before CLKIN 6 + DT/2 ns
Switching Characteristics
t
MIENA
Address/Select Enable After CLKIN
1
–1.5 – DT/8 ns
t
MIENS
Strobes Enable After CLKIN
2
–1.5 – DT/8 ns
t
MIENHG
HBG Enable After CLKIN –1.5 – DT/8 ns
t
MITRA
Address/Select Disable After CLKIN
3
0 – DT/4 ns
t
MITRS
Strobes Disable After CLKIN
2
1.5 – DT/4 ns
t
MITRHG
HBG Disable After CLKIN 2.0 – DT/4 ns
t
DATEN
Data Enable After CLKIN
4
9 + 5DT/16 ns
t
DATTR
Data Disable After CLKIN
4
0 – DT/8 7 – DT/8 ns
t
ACKEN
ACK Enable After CLKIN
4
7.5 + DT/4 ns
t
ACKTR
ACK Disable After CLKIN
4
–1 – DT/8 6 – DT/8 ns
t
ADCEN
ADRCLK Enable After CLKIN –2 – DT/8 ns
t
ADCTR
ADRCLK Disable After CLKIN 8 – DT/4 ns
t
MTRHBG
Memory Interface Disable Before HBG Low
5
0 + DT/8 ns
t
MENHBG
Memory Interface Enable After HBG High
5
19 + DT ns
1
For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min.
2
Strobes = RD, WR, PAGE, DMAG, BMS, SW.
3
For ADSP-21060LC, specification is 0.25 – DT/4 ns max.
4
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
5
Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode).
Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
MEMORY
INTERFACE
HBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW,PAGE,DMAGx. BMS (IN EPROM BOOT MODE)
t
MENHBG
t
MTRHBG