Datasheet

Rev. F | Page 36 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx
is used to initiate transfers. For
Handshake mode, DMAGx
controls the latching or enabling of
data externally. For External handshake mode, the data transfer
is controlled by the ADDR31–0, RD
, WR, PAGE, MS3–0, ACK,
and DMAG
x signals. For Paced Master mode, the data transfer
is controlled by ADDR31–0, RD
, WR, MS3–0, and ACK (not
DMAG
). For Paced Master mode, the Memory Read-Bus Mas-
ter, Memory Write-Bus Master, and Synchronous Read/Write-
Bus Master timing specifications for ADDR31–0, RD
, WR,
MS3–0
, PAGE, DATA63–0, and ACK also apply.
Table 22. DMA Handshake
5 V and 3.3 V
Unit
Parameter Min Max
Timing Requirements
t
SDRLC
DMARx Low Setup Before CLKIN
1
5ns
t
SDRHC
DMARx High Setup Before CLKIN
1
5ns
t
WDR
DMARx Width Low (Nonsynchronous) 6 ns
t
SDATDGL
Data Setup After DMAGx Low
2
10 + 5DT/8 ns
t
HDATIDG
Data Hold After DMAGx High 2 ns
t
DATDRH
Data Valid After DMARx High
2
16 + 7DT/8 ns
t
DMARLL
DMARx Low Edge to Low Edge 23 + 7DT/8 ns
t
DMARH
DMARx Width High
2
6ns
Switching Characteristics
t
DDGL
DMAGx Low Delay After CLKIN 9 + DT/4 15 + DT/4 ns
t
WDGH
DMAGx High Width 6 + 3DT/8 ns
t
WDGL
DMAGx Low Width 12 + 5DT/8 ns
t
HDGC
DMAGx High Delay After CLKIN –2 – DT/8 6 – DT/8 ns
t
VDATDGH
Data Valid Before DMAGx High
3
8 + 9DT/16 ns
t
DATRDGH
Data Disable After DMAGx High
4
07ns
t
DGWRL
WR Low Before DMAGx Low
5
02ns
t
DGWRH
DMAGx Low Before WR High 10 + 5DT/8 +W ns
t
DGWRR
WR High Before DMAGx High 1 + DT/16 3 + DT/16 ns
t
DGRDL
RD Low Before DMAGx Low 0 2 ns
t
DRDGH
RD Low Before DMAGx High 11 + 9DT/16 + W ns
t
DGRDR
RD High Before DMAGx High 0 3 ns
t
DGWR
DMAGx High to WR, RD, DMAGx Low 5 + 3DT/8 + HI ns
t
DADGH
Address/Select Valid to DMAGx High 17 + DT ns
t
DDGHA
Address/Select Hold After DMAGx High
6
–0.5 ns
W = (number of wait states specified in WAIT register) ⴛ t
CK
.
HI = t
CK
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
be driven t
DATDRH
after DMARx is brought high.
3
t
VDATDGH
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
VDATDGH
=t
CK
–0.25t
CCLK
–8+(n×t
CK
) where n equals
the number of extra cycles that the access is prolonged.
4
See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
5
For ADSP-21062/ADSP-21062L specification is –2.5 ns min, 2 ns max.
6
For ADSP-21060L/ADSP-21062L specification is –1 ns min.