Datasheet
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F | Page 41 of 64 | March 2008
Figure 24. Link Ports—Receive
CLKIN
LCLK
LDAT(3:0)
LACK
LCLK 1x
OR
LCLK 2x
CLKIN
LDAT(3:0)
LACK (IN)
LCLK 1x
OR
LCLK 2x
LDAT(3:0)
LACK (OUT)
THE
t
SLACH
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
CLKIN
TRANSMIT
t
DLDCH
t
HLDCH
t
DLCLK
t
LCLKTWH
t
LCLKTWL
t
SLACH
t
HLACH
t
DLACLK
t
SLDCL
t
HLDCL
t
LCLKRWH
t
DLAHC
t
DLALC
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
t
ENDLK
t
TDLK
RECEIVE
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
t
LCLKRWL
t
LCLKIW
CLKIN
t
SLCK
t
HLCK
LINK PORT INTERRUPT SETUP TIME
LCLK
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
OUT
IN
LACK