Datasheet

Rev. F | Page 4 of 64 | March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
GENERAL DESCRIPTION
The ADSP-2106x SHARC
®
—Super Harvard Architecture Com-
puter—is a 32-bit signal processing microcomputer that offers
high levels of DSP performance. The ADSP-2106x builds on the
ADSP-21000 DSP core to form a complete system-on-a-chip,
adding a dual-ported on-chip SRAM and integrated I/O periph-
erals supported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 2 shows perfor-
mance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including up to 4M bit
SRAM memory (see Table 1), a
host processor interface, DMA controller, serial ports and link
port, and parallel bus connectivity for glueless DSP
multiprocessing.
The ADSP-2106x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram on Page 1 illustrates the following architec-
tural features:
• Computation units (ALU, multiplier and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Interval timer
•On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor Interface
• DMA controller
• Serial ports and link ports
• JTAG Test Access Port
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-2106x processors
are code- and function-compatible with the ADSP-21020.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general–purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Table 2. Benchmarks (at 40 MHz)
Benchmark Algorithm Speed Cycles
1024 Point Complex FFT (Radix 4, with
reversal)
0.46 Ps 18,221
FIR Filter (per tap) 25 ns 1
IIR Filter (per biquad) 100 ns 4
Divide (y/x) 150 ns 6
Inverse Square Root 225 ns 9
DMA Transfer Rate 240 Mbytes/s
Figure 2. ADSP-2106x System Sample Configuration
3
4
RESET JTAG
6
ADSP-2106x
BMS
1 ⫻ CLOCK
LINK
DEVICES
(6 MAX)
(OPTIONAL)
CS
BOOT
EPROM
(OPTIONAL)
MEMORY-
MAPPED
DEVICES
(OPTIONAL)
OE
DATA
DMA DEVICE
(OPT IONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
CS
RD
PAGE
ADRCLK
ACK
BR1–6
DMAR1–2
CLKIN
IRQ2–0
LxCLK
TCLK0
RPBA
EBOOT
LBOOT
FLAG3–0
TIMEXP
LxACK
LxDAT3–0
DR0
DT0
RSF0
TFS0
RCLK0
TCLK1
DR1
DT1
RSF1
TFS1
RCLK1
ID2–0
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
PA
REDY
HBG
HBR
DMAG1–2
SBTS
MS3–0
WR
DATA47–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
D
A
T
A
C
O
N
T
R
O
L
A
D
D
R
E
S
S
ADDR