Datasheet

ManualsBrandsANALOG DEVICES ManualsMicrocontrollers, Microprocessors & QuartzesDigital signal processor (DSP) MQFP 240 EP (32x32) 3.3 V 40 MHz

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SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. F

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SUMMARY

High performance signal processor for communications,

graphics and imaging applications

Super Harvard Architecture

4 independent buses for dual data fetch, instruction fetch,

and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip

Integrated multiprocessing features

240-lead thermally enhanced MQFP_PQ4 package, 225-ball

plastic ball grid array (PBGA), 240-lead hermetic CQFP

package

RoHS compliant packages

KEY FEATURES—PROCESSOR CORE

40 MIPS, 25 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse

addressing)

Efficient program sequencing with zero-overhead looping:

Single-cycle loop setup

IEEE JTAG Standard 1149.1 Test Access Port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format

Figure 1. Functional Block Diagram

MULT

BARREL

SERIAL PORTS

(2)

LINK PORTS

(6)

IOP

REGISTERS

(MEMORY

MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

I/O PROCESSOR

TIMER

INSTRUCTION

CACHE

ADDR DATA

DATA ADDR

ADDR DATA ADDR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

DUAL-PORTED SRAM

JTAG

TEST AND

EMULATION

HOST PORT

ADDR BUS

MUX

IOA

IOD

MULTIPROCESSOR

INTERFACE

EXTERNAL

PORT

DATA BUS

MUX

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DAG1

40/32

CORE PROCESSOR

PROGRAM

SEQUENCER

BLOCK 0

BLOCK 1

8  4  32

DAG2

8  4  24

32  48-BIT

PM ADDRESS BUS

DATA

CONTROLLER

DMA

DATA

FILE

16  40-BIT

ALU

SHIFTER

Summary of content (64 pages)

PAGE 1
SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY KEY FEATURES—PROCESSOR CORE High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing featur
PAGE 2
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PROCESSOR FEATURES (Continued) The processor family provides a variety of features. For a comparison across family members, see Table 1.
PAGE 3
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CONTENTS Summary ............................................................... 1 ADSP-21060/ADSP-21062 Specifications ..................... 15 Key Features—Processor Core .................................... 1 Operating Conditions (5 V) ................................... 15 Processor Features (Continued) .................................. 2 Electrical Characteristics (5 V) ................................
PAGE 4
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC GENERAL DESCRIPTION The ADSP-2106x SHARC®—Super Harvard Architecture Computer—is a 32-bit signal processing microcomputer that offers high levels of DSP performance. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
PAGE 5
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Single-Cycle Fetch of Instruction and Two Operands The ADSP-2106x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1).
PAGE 6
ADDRESS DATA DATA RESET ADDRESS ADSP-2106x #3 CLKIN CONTROL ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 CONTROL ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADDR31–0 DATA47–0 RPBA 3 ID2–0 CONTROL 011 BR1–2, BR4–6 5 BR3 ADSP-2106x #2 CLKIN ADDR31–0 RESET DATA47–0 RPBA 3 ID2–0 CONTROL 010 CPA BR1, BR3–6 BR2 5 ADSP-2106x #1 CLKIN RESET ADDR31–0 ADDR DATA47–0 DATA RPBA ID2–0 001 BUS PRIORITY RESET CLOCK CONTROL 3 OE WE RDx WRx ACK MS3–0 GLOBAL MEMORY A
PAGE 7
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC control two DMA channels using DMA request/grant lines (DMAR1–2, DMAG1–2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers. DMA Controller The ADSP-2106x’s on-chip DMA controller allows zero-overhead data transfers without processor intervention.
PAGE 8
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports The ADSP-2106x features six 4-bit link ports that provide additional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. Linkport I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously, with a maximum data throughput of 240M bytes/s.
PAGE 9
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.
PAGE 10
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PIN FUNCTION DESCRIPTIONS The ADSP-2106x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).
PAGE 11
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin ACK Type I/O/S Function Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous access of its internal memory.
PAGE 12
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin TFSx RFSx LxDAT3–0 Type I/O I/O I/O Function Transmit Frame Sync (Serial Ports 0, 1). Receive Frame Sync (Serial Ports 0, 1). Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k: internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register. LxCLK I/O Link Port Clock (Link Ports 0–5).
PAGE 13
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TARGET BOARD CONNECTOR FOR EZ-ICE PROBE The ADSP-2106x EZ-ICE® Emulator uses the IEEE 1149.1JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2-row 7-pin strip header) such as that shown in Figure 5.
PAGE 14
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EM U EMU TR ST TRST TDO TDI TCK TRST TMS TCK EMU TDO TDI TRST TCK EZ-ICE JTAG CONNECTOR OTHER JTAG CONTROLLER TDO TDI TMS TDI ADSP-2106x n TMS JTAG DEVICE (OPTIONAL) ADSP-2106x #1 TCK TMS EMU TRST TDO CLKIN OPTIONAL Figure 6.
PAGE 15
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060/ADSP-21062 SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (5 V) A Grade Parameter VDD TCASE VIH11 VIH22 VIL 1, 2 Description Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = Max High Level Input Voltage @ VDD = Max Low Level Input Voltage @ VDD = Min Min 4.75 –40 2.0 2.2 –0.5 Max 5.25 +85 VDD + 0.5 VDD + 0.5 +0.8 C Grade Min 4.
PAGE 16
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (5 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation Measurements.” Specifications are based on the operating scenarios.
PAGE 17
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (5 V) Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: drive high and low at a maximum rate of 1/(2tCK).
PAGE 18
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060L/ADSP-21062L SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (3.3 V) A Grade Parameter VDD TCASE VIH11 VIH22 VIL 1, 2 Description Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = Max High Level Input Voltage @ VDD = Max Low Level Input Voltage @ VDD = Min Min 3.15 –40 2.0 2.2 –0.5 C Grade Max 3.45 +85 VDD + 0.5 VDD + 0.5 +0.8 Min 3.
PAGE 19
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (3.3 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation Measurements.” Specifications are based on the operating scenarios.
PAGE 20
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (3.3 V) drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers.
PAGE 21
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ESD CAUTION TIMING SPECIFICATIONS ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
PAGE 22
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Clock Input Table 9. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 1 ADSP-21060 ADSP-21062 40 MHz, 5 V Min Max ADSP-21060 ADSP-21062 33 MHz, 5 V Min Max ADSP-21060L ADSP-21062L 40 MHz, 3.3 V Min Max ADSP-21060L ADSP-21062L 33 MHz, 3.3 V Min Max 25 7 5 30 7 5 25 8.75 5 30 8.
PAGE 23
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Interrupts Table 11. Interrupts Parameter Timing Requirements tSIR IRQ2–0 Setup Before CLKIN High1 tHIR IRQ2–0 Hold Before CLKIN High1 tIPW IRQ2–0 Pulse Width2 1 2 5 V and 3.3 V Max Min 18 + 3DT/4 12 + 3DT/4 2+tCK Unit ns ns ns Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met. CLKIN tSIR tHIR IRQ2–0 tIPW Figure 11. Interrupts Timer Table 12.
PAGE 24
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Flags Table 13. Flags Parameter Timing Requirements tSFI FLAG3–0 IN Setup Before CLKIN High1 tHFI FLAG3–0 IN Hold After CLKIN High1 tDWRFI FLAG3–0 IN Delay After RD/WR Low1 tHFIWR FLAG3–0 IN Hold After RD/WR Deasserted1 Switching Characteristics tDFO FLAG3–0 OUT Delay After CLKIN High tHFO FLAG3–0 OUT Hold After CLKIN High tDFOE CLKIN High to FLAG3–0 OUT Enable tDFOD CLKIN High to FLAG3–0 OUT Disable 1 Min 5 V and 3.
PAGE 25
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and DMAGx strobe timing parameters only applies to asynchronous access mode. Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 14. Memory Read—Bus Master 5 V and 3.
PAGE 26
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and DMAGx strobe timing parameters only applies to asynchronous access mode. Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 15. Memory Write—Bus Master 5 V and 3.
PAGE 27
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read—Bus Master on Page 25 and Memory Write— Bus Master on Page 26).
PAGE 28
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tADRCK tDADCCK tADRCKH tDADRO tDAAK tADRCKL ADDRCLK tHADRO ADDRESS, BMS, SW, MSx tDPGC PAGE tHACK tSACKC ACK (IN) READ CYCLE tDRWL tDRDO RD tSSDATI tHSDATI DATA (IN) WRITE CYCLE tDWRO tDRWL WR tDATTR tSDDATO DATA (OUT) Figure 16. Synchronous Read/Write—Bus Master Rev.
PAGE 29
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Synchronous Read/Write—Bus Slave Use these specifications for bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet the bus slave timing requirements. Table 17.
PAGE 30
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-2106xs (BRx) or a host processor, both synchronous and asynchronous (HBR, HBG). Table 18.
PAGE 31
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSH B R I tH H B R I HBR tD HB GO tH H B GO HBG (OUT) tD B R O tH B R O BRx (OUT) tTRC P A tD C PA O CPA (OUT, O/D) tSH B GI tH H B GI HBG (I N) tSB R I tH B R I BRx, CPA (IN, O/ D) tS R PB A I tH R PB A I RPBA HBR CS tTR D YH G tD RD Y C S REDY (O/D) tA R DY TR REDY (A/D) tH B GR C SV HBG (OUT) RD WR CS O/D = O PEN DRAIN, A/D = ACTIVE DRIVE Figure 18. Multiprocessor Bus Request and Host Bus Request Rev.
PAGE 32
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Asynchronous Read/Write—Host to ADSP-2106x Use these specifications for asynchronous host processor accesses of an ADSP-2106x, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-2106x, the host can drive the RD and WR pins to access the ADSP-2106x’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. Not required if and address are valid tHBGRCSV after goes low.
PAGE 33
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN t SR D YC K REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 19.
PAGE 34
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Three-State Timing—Bus Master/ Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 21.
PAGE 35
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSTSCK tHTSCK SBTS tMIENA, tMIENS, tMIENHG tMITRA, tMITRS, tMITRHG MEMORY INTERFACE tDATTR tDATEN DATA tACKTR tACKEN ACK tADCEN tADCTR ADRCLK Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) Rev.
PAGE 36
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DMA Handshake These specifications describe the three DMA handshake modes. In all three modes, DMARx is used to initiate transfers. For Handshake mode, DMAGx controls the latching or enabling of data externally. For External handshake mode, the data transfer is controlled by the ADDR31–0, RD, WR, PAGE, MS3–0, ACK, and DMAGx signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not DMAG).
PAGE 37
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSDRLC tDMARLL tSDRHC tWDR tDMARH DMARx tHDGC tDDGL tWDGL tWDGH DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE tDATRDGH tVDATDGH DATA (OUT) (FROM ADSP-2106x TO EXTERNAL DEVICE) tDATDRH tSDATDGL DATA (IN) tHDATIDG (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) tDGWRL WR tDGWRH tDGWRR (EXTERNAL DEVICE TO EXTERNAL MEMORY)
PAGE 38
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports —1 × CLK Speed Operation Table 23. Link Ports—Receive Parameter Timing Requirements tSLDCL Data Setup Before LCLK Low1 Data Hold After LCLK Low tHLDCL tLCLKIW LCLK Period (1u Operation) tLCLKRWL LCLK Width Low tLCLKRWH LCLK Width High Switching Characteristics tDLAHC LACK High Delay After CLKIN High2, 3 LACK Low Delay After LCLK High tDLALC tENDLK LACK Enable From CLKIN tTDLK LACK Disable From CLKIN 5V Max Min 3.
PAGE 39
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 25. Link Port Service Request Interrupts:1u and 2u Speed Operations Parameter Timing Requirements tSLCK LACK/LCLK Setup Before CLKIN Low1 tHLCK LACK/LCLK Hold After CLKIN Low1 1 5V Max Min 10 2 Min 3.3 V Max 10 2 Unit ns ns Only required for interrupt recognition in the current cycle.
PAGE 40
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 27. Link Ports—Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK High tHLACH LACK Hold After LCLK High Switching Characteristics tDLCLK Data Delay After CLKIN tDLDCH Data Delay After LCLK High1 tHLDCH Data Hold After LCLK High2 tLCLKTWL LCLK Width Low3 LCLK Width High4 tLCLKTWH tDLACLK LCLK Low Delay After LACK High Min 5V Max 19 –6.75 Min 19 –6.5 8 2.25 –2.0 (tCK /4) – 1 (tCK /4) – 1.25 (tCK /4) + 9 3.
PAGE 41
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TRANSMIT CLKIN tDLCLK tLCLKTWH tLCLKTWL LAST NIBBLE TRANSMITTED FIRST NIBBLE TRANSMITTED LCLK 1x OR LCLK 2x LCLK INACTIVE (HIGH) tDLDCH tHLDCH LDAT(3:0) OUT tDLACLK tSLACH tHLACH LACK (IN) THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
PAGE 42
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Serial Ports For serial ports, see Table 28, Table 29, Table 30, Table 31, Table 32, Table 33, Table 35, Figure 26, and Figure 25. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 28.
PAGE 43
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 32. Serial Ports—Internal Clock Parameter Switching Characteristics tDFSI TFS Delay After TCLK (Internally Generated TFS)1 TFS Hold After TCLK (Internally Generated TFS)1 tHOFSI tDDTI Transmit Data Delay After TCLK1 tHDTI Transmit Data Hold After TCLK1 tSCLKIW TCLK/RCLK Width2 1 2 Min Max Unit 4.5 0 0.5tSCLK –2.5 0.5tSCLK +2.5 ns ns ns ns ns Min Max Unit –1.5 7.5 Referenced to drive edge.
PAGE 44
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKW tSCLKIW RCLK RCLK tDFSE tDFSE tSFSI tHOFSE tHOFSE tHFSI RFS tSFSE tHFSE tSDRE tHDRE RFS tSDRI tHDRI DR DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
PAGE 45
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RCLK tSFSE/I tHOFSE/I RFS tDDTE/I tHDTE/I tDDTENFS DT 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK tHOFSE/I tSFSE/I TFS tDDTE/I TDDTENFS DT tHDTE/I 1ST BIT 2ND BIT tDDTLFSE Figure 26. Serial Ports—External Late Frame Sync Rev.
PAGE 46
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC JTAG Test Access Port and Emulation For JTAG Test Access Port and Emulation, see Table 36 and Figure 27. Table 36.
PAGE 47
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TEST CONDITIONS For the ac signal specifications (timing parameters), see Timing Specifications on Page 21. These specifications include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 28. INPUT OR OUTPUT 1.5V 1.5V Figure 28.
PAGE 48
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics (5 V) 3.5 RISE AND FALL TIMES - ns (0.8V to 2.0V) 75 SOURCE CURRENT - mA 50 25 5.25V, -40°C 5.0V, +25°C 0 4.75V, +100°C -25 4.75V,+100°C -50 5.0V, +25°C -75 5.25V, -40°C -100 -125 -150 0 2.5 RISE TIME 2.0 Y = 0.009x + 1.1 1.5 FALL TIME 1.0 Y = 0.005x + 0.6 0.5 0 0.75 1.50 2.25 3.00 3.75 SOURCE VOLTAGE - V 4.50 0 5.25 20 40 60 80 100 120 140 LOAD CAPACITANCE - pF 160 180 200 Figure 33.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics (3.3 V) 18 3.3V, +25°C 80 SOURCE CURRENT - mA RISE AND FALL TIMES - ns (10% to 90%) 100 3.6V, -40°C 60 40 3.0V, +85°C VOH 20 0 3.0V, +85°C 3.3V, +25°C -40 3.6V, -40°C -60 16 14 Y = 0.0796x + 1.17 12 10 RISE TIME 8 6 FALL TIME 2 VOL -100 Y = 0.0467x + 0.55 4 0 -120 0.5 1.0 1.5 2.0 2.5 0 3.0 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE - pF Figure 37.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ENVIRONMENTAL CONDITIONS Thermal Characteristics for CQFP Package The ADSP-2106x processors are rated for performance under TCASE environmental conditions specified in the Operating Conditions (5 V) on Page 15 and Operating Conditions (3.3 V) on Page 18. The ADSP-21060C/ADSP-21060LC are available in 240-lead thermally enhanced ceramic QFP (CQFP).
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 225-BALL PBGA BALL CONFIGURATIONS Table 40.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 15 14 13 12 11 10 9 DATA47 BR3 PAGE CLKIN CS DATA39 DATA43 DATA45 BR2 BR6 ACK RD REDY DATA36 DATA38 DATA41 DATA46 BR4 DMAG1 WR DATA34 DATA35 DATA37 DATA40 BR1 BR5 DATA42 DATA44 8 7 6 ADRCLK RCLK0 5 4 3 2 BMS A SW MS0 B MS1 MS3 C DMAR2 ADDR30 TCLK0 RCLK1 DT1 DR0 DT0 DR1 HBR ADDR31 RFS0 TFS0 RFS1 TCLK1 SBTS ADDR28 DMAG2 HBG CPA TFS1 DMAR1 ADDR29 MS2 GND 1 ADDR26 ADDR25
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATIONS Table 41. ADSP-2106x MQFP_PQ4, ADSP-21060CW, and ADSP-21060LCW CQFP Pin Assignments (SP-240-2, QS-240-2) Pin Name TDI TRST VDD TDO TIMEXP EMU ICSA FLAG3 FLAG2 FLAG1 FLAG0 GND ADDR0 ADDR1 VDD ADDR2 ADDR3 ADDR4 GND ADDR5 ADDR6 ADDR7 VDD ADDR8 ADDR9 ADDR10 GND ADDR11 ADDR12 ADDR13 VDD ADDR14 ADDR15 GND ADDR16 ADDR17 ADDR18 VDD VDD ADDR19 Pin No.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 42. ADSP-21060CZ/21060LCZ CQFP Pin Assignments (QS-240-1) Pin Name GND DATA0 DATA1 DATA2 VDD DATA3 DATA4 DATA5 GND DATA6 DATA7 DATA8 VDD DATA9 DATA10 DATA11 GND DATA12 DATA13 DATA14 VDD DATA15 DATA16 DATA17 GND DATA18 DATA19 DATA20 VDD DATA21 DATA22 DATA23 GND DATA24 DATA25 DATA26 VDD VDD DATA27 DATA28 Pin No.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OUTLINE DIMENSIONS 23.20 23.00 SQ 22.80 A1 CORNER INDEX AREA 15 13 11 9 7 5 3 1 14 12 10 8 6 4 2 A B C D E F G H J K L M N P R BALL A1 INDICATOR 20.10 20.00 SQ 19.90 TOP VIEW 18.00 BSC SQ 1.27 BSC 0.50 R 3 PLACES BOTTOM VIEW DETAIL A 2.70 MAX DETAIL A 0.70 0.60 0.50 SEATING PLANE 0.15 MAX COPLANARITY 0.90 0.75 0.60 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2 Figure 40.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 34.60 BSC SQ 0.66 0.56 0.46 29.50 REF SQ 4.10 3.78 3.55 181 240 1 180 SEATING PLANE PIN 1 24.00 REF SQ HEAT SLUG TOP VIEW (PINS DOWN) 32.00 BSC SQ 121 60 3.50 3.40 3.30 0.20 0.09 0.38 0.25 7° 0° VIEW A 0.076 COPLANARITY 120 61 0.50 BSC LEAD PITCH 3.92 u 45° (4 PLACES) 0.27 MAX 0.17 MIN VIEW A ROTATED 90° CCW COMPLIANT WITH JEDEC STANDARDS MS-029-GA Figure 41.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 28.05 27.80 SQ 27.55 32.00 BSC SQ PIN 1 INDICATOR 181 240 181 240 1 180 180 1 SEAL RING LID TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) HEAT SLUG 121 60 61 4.30 3.62 2.95 3.70 3.22 2.75 0.90 0.75 0.60 0.23 0.20 0.17 60 120 61 VIEW A 19.00 REF SQ 7° -3° 121 120 0.50 BSC 0.60 0.40 0.20 1.70 0.15 0.35 0.30 0.25 0.175 0.156 0.137 NOTES: 1. LEAD FINISH = GOLD PLATE 2.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 2.60 2.55 2.50 75.00 BSC SQ 29.50 BSC 16.50 (8×) 2.05 3.60 3.55 3.50 120 120 61 61 121 121 60 60 SEAL RING LID 65.90 BSC 29.50 BSC TOP VIEW BOTTOM VIEW HEAT SLUG 1 1 180 240 INDEX 1 181 INDEX 2 1.50 DIA NO GOLD GOLD PLATED 240 1.22 (4×) NONCONDUCTIVE CERAMIC TIE BAR 70.00 BSC SQ 75.50 BSC SQ 0.50 3.42 3.17 2.92 0.90 0.80 0.70 SIDE VIEW Figure 43.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 19.00 REF SQ 32.00 BSC SQ PIN 1 INDICATOR 181 240 181 240 1 180 180 1 SEAL RING LID TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) HEAT SLUG 121 60 61 28.05 27.80 SQ 27.55 4.20 3.52 2.85 7° -3° 121 0.90 0.75 0.60 0.23 0.20 0.17 60 120 120 61 VIEW A 3.70 3.22 2.75 0.50 BSC 0.50 0.30 0.10 1.70 0.15 0.35 0.30 0.25 0.175 0.156 0.137 NOTES: 1. LEAD FINISH = GOLD PLATE 2.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 2.60 2.55 2.50 75.00 BSC SQ 29.50 BSC 16.50 (8×) 2.05 3.60 3.55 3.50 120 120 61 61 121 121 60 60 SEAL RING LID 65.90 BSC 29.50 BSC TOP VIEW BOTTOM VIEW HEAT SLUG 240 INDEX 1 181 180 1 1 180 INDEX 2 2.00 DIA NO GOLD GOLD PLATED 240 181 1.22 (4×) NONCONDUCTIVE CERAMIC TIE BAR 70.00 BSC SQ 75.50 BSC SQ 0.50 3.42 3.17 2.92 0.90 0.80 0.70 SIDE VIEW Figure 45.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ORDERING GUIDE Model ASDP-21060CZ-1331 ASDP-21060CZZ-1331, 2 ASDP-21060CZ-1601 ASDP-21060CZZ-1601, 2 ASDP-21060CW-1331 ASDP-21060CWZ-1331, 2 ASDP-21060CW-1601 ASDP-21060CWZ-1601, 2 ADSP-21060KS-133 ADSP-21060KSZ-1332 ADSP-21060KS-160 ADSP-21060KSZ-1602 ADSP-21060KB-160 ADSP-21060KBZ-1602 ADSP-21060LKS-133 ADSP-21060LKSZ-1332 ADSP-21060LKS-160 ADSP-21060LKSZ-1602 ADSP-21060LKB-160 ADSP-21060LKBZ-1602 ADSP-21060LAB-160 ADSP-21060LABZ-1602
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev.
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00167-0-3/08(F) Rev.