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REV. 0
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
a
S
DSP Microcomputer
ADSP-21160N
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4 M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
FUNCTIONAL BLOCK DIAGRAM
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16  40-BIT
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEX)
16  40-BIT
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
60
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
I/O PROCESSOR
DMA
CONTROLLER
TIMER
INSTRUCTION
CACHE
32  48-BIT
ADDR DATA
DATA
DATA
ADDR
ADDR DATA ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
6
HOST PORT
ADDR BUS
MUX
IOA
18
IOD
64
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
64
32
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
8  4  32
32
16/32/40/48/64
32/40/64
CORE PROCESSOR
PROGRAM
SEQUENCER
DAG2
8  4  32
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